Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms

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Multi-scenario high-level synthesis for distributed register/controller architecture has been proposed targeting static delay variation. In this paper, we extend it and propose a floorplan-driven high-level synthesis algorithm which can be applied to dynamic delay variation by effectively using an error prediction technique, where pre-error registers are introduced to local registers in every circuit block. Experimental results show that the proposed algorithm using two and three scenarios on an FPGA chip reduces the average number of required control steps by 17.6% and 25.5% on average compared to worst-case high-level synthesis at the expense of increasing lookup-tables and flip-flops. Moreover, we implement a multi-scenario elliptic-wave-filter (EWF) circuit with three scenarios synthesized by our proposed algorithm onto an FPGA chip and run it under the environment with varying supply voltages which causes dynamic delay variation. The FPGA implementation experiments also demonstrate that the EWF circuit effectively runs on the real FPGA chip. As far as we know, this is the world-first experiment where a multi-scenario circuit runs under real dynamic delay variation environment.

Original languageEnglish
Article number20160641
Journalieice electronics express
Issue number18
Publication statusPublished - 2016


  • Adaptive behavior
  • Distributed register/controller architecture
  • Dynamic delay variation
  • High-level synthesis

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering


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