TY - GEN
T1 - Multigrain parallel processing for JPEG encoding on a single chip multiprocessor
AU - Kodaka, T.
AU - Kimura, K.
AU - Kasahara, H.
N1 - Publisher Copyright:
© 2002 IEEE.
PY - 2002
Y1 - 2002
N2 - With the recent increase of multimedia content using JPEG and MPEG, low cost, low power consumption and high performance processors for multimedia application are desirable. In particular, single chip multiprocessor architecture having simple processor cores that will attain good scalability and cost effectiveness is attracting much attention. To exploit full performance of single chip multiprocessor architecture, multigrain parallel processing, which exploits coarse grain task parallelism, loop parallelism and instruction level parallelism, is attractive. This paper describes a multigrain parallel processing scheme for JPEG encoding on a single chip multiprocessor and its performance. The evaluation shows that an OSCAR type single chip multiprocessor having four single-issue simple processor cores gave a 3.59 times speed-up against sequential execution time.
AB - With the recent increase of multimedia content using JPEG and MPEG, low cost, low power consumption and high performance processors for multimedia application are desirable. In particular, single chip multiprocessor architecture having simple processor cores that will attain good scalability and cost effectiveness is attracting much attention. To exploit full performance of single chip multiprocessor architecture, multigrain parallel processing, which exploits coarse grain task parallelism, loop parallelism and instruction level parallelism, is attractive. This paper describes a multigrain parallel processing scheme for JPEG encoding on a single chip multiprocessor and its performance. The evaluation shows that an OSCAR type single chip multiprocessor having four single-issue simple processor cores gave a 3.59 times speed-up against sequential execution time.
KW - Application software
KW - Computer architecture
KW - Concurrent computing
KW - Costs
KW - Encoding
KW - Energy consumption
KW - Parallel processing
KW - Power engineering and energy
KW - Power engineering computing
KW - Scalability
UR - http://www.scopus.com/inward/record.url?scp=84948681716&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84948681716&partnerID=8YFLogxK
U2 - 10.1109/IWIA.2002.1035019
DO - 10.1109/IWIA.2002.1035019
M3 - Conference contribution
AN - SCOPUS:84948681716
T3 - Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems
SP - 57
EP - 63
BT - International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2002
A2 - Joe, Kazuki
A2 - Veidenbaum, Alex
PB - IEEE Computer Society
T2 - International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, IWIA 2002
Y2 - 11 January 2002
ER -