In this paper we propose a new reseeding method for LFSR-based test pattern generation suitable for circuits with random pattern resistant faults. The character of our method is that the proposed test pattern generator (TPG) can work both in normal LFSR mode, to generate pseudorandom test vectors, and in jumping mode to make the TPG jump from a state to the required state (seed of next group). Experimental results indicate that its superiority against other known reseeding techniques with respect to the length of the test sequence and the required area overhead.
|Title of host publication
|Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
|Institute of Electrical and Electronics Engineers Inc.
|Number of pages
|Published - 2003
|Asia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: 2003 Jan 21 → 2003 Jan 24
|Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
|Asia and South Pacific Design Automation Conference, ASP-DAC 2003
|03/1/21 → 03/1/24
ASJC Scopus subject areas
- Computer Science Applications
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering