N bit-wise modular multiplier architecture for public key cryptography

Tohru Hisakado*, Nobuyuki Kobayashi, Takeshi Ikenaga, Takaaki Baba, Satoshi Goto, Kunihiko Higashi, Ichiro Kitao, Yukiyasu Tsunoo

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)


Along with the progress of the information society, we are relying more and more on digital information processing with security. Cryptography plays an important role in a situation where unwanted eavesdropping or falsification has to be avoided. Public key encryptions including RSA require a huge number of arithmetic operations. Major part of its operation is modular multiplication with very large bit-width. This operation takes long time, and there is an advantage in hardware implementation of it. We propose the hardware implementation of N-bit-wise multiplier. It allows the operation performed at the speed 2 times the original performance for the same circuit size, or the circuit size reduced to approximately 60% for the same processing time. Employing the architecture proposed in this paper contributes to the performance improvement of encryption system and the reduction of chip size of encryption system.

Original languageEnglish
Pages (from-to)221-225
Number of pages5
JournalProceedings - International Carnahan Conference on Security Technology
Publication statusPublished - 2004
EventProceedings - IEEE 38th Annual 2004 International Carnahan Conference on Security Technology - Albuquerque, NM, United States
Duration: 2004 Oct 112004 Oct 14

ASJC Scopus subject areas

  • Engineering(all)


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