Network on chip architecture for BP neural network

Yiping Dong; Takahiro Watanabe

doi:10.1109/ICCCAS.2008.4657930

Network on chip architecture for BP neural network

Yiping Dong^*, Takahiro Watanabe

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

Recently, Networks-on-Chips (NoCs) have a great development and have been proposed as a promising solution to complex on-chip communication problems. One of the problems is an application of Artificial Neural Networks (ANNs). In this paper, we propose NoCs for the ANNs. NoCs is designed to implement a BP-ANNs (Back-Propagation) and evaluated by Network-on-Chips. Experimental results show that for has a great reduction in communication load and a high connection per second (CPS) compared with traditional BP-ANNs. It is also reconfigurable, expandable and stable to meet various problems.

Original language	English
Title of host publication	2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
Pages	964-968
Number of pages	5
DOIs	https://doi.org/10.1109/ICCCAS.2008.4657930
Publication status	Published - 2008
Externally published	Yes
Event	2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008 - Xiamen, Fujian Province, China Duration: 2008 May 25 → 2008 May 27

Publication series

Name	2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008

Conference

Conference	2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
Country/Territory	China
City	Xiamen, Fujian Province
Period	08/5/25 → 08/5/27

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

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10.1109/ICCCAS.2008.4657930

Cite this

Network on chip architecture for BP neural network. / Dong, Yiping; Watanabe, Takahiro.
2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008. 2008. p. 964-968 4657930 (2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Dong, Y & Watanabe, T 2008, Network on chip architecture for BP neural network. in 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008., 4657930, 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008, pp. 964-968, 2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008, Xiamen, Fujian Province, China, 08/5/25. https://doi.org/10.1109/ICCCAS.2008.4657930

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abstract = "Recently, Networks-on-Chips (NoCs) have a great development and have been proposed as a promising solution to complex on-chip communication problems. One of the problems is an application of Artificial Neural Networks (ANNs). In this paper, we propose NoCs for the ANNs. NoCs is designed to implement a BP-ANNs (Back-Propagation) and evaluated by Network-on-Chips. Experimental results show that for has a great reduction in communication load and a high connection per second (CPS) compared with traditional BP-ANNs. It is also reconfigurable, expandable and stable to meet various problems.",

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AU - Watanabe, Takahiro

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AB - Recently, Networks-on-Chips (NoCs) have a great development and have been proposed as a promising solution to complex on-chip communication problems. One of the problems is an application of Artificial Neural Networks (ANNs). In this paper, we propose NoCs for the ANNs. NoCs is designed to implement a BP-ANNs (Back-Propagation) and evaluated by Network-on-Chips. Experimental results show that for has a great reduction in communication load and a high connection per second (CPS) compared with traditional BP-ANNs. It is also reconfigurable, expandable and stable to meet various problems.

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Network on chip architecture for BP neural network

Abstract

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Conference

ASJC Scopus subject areas

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