New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS)

S. Kobayashi; M. Edahiro; Y. Hayashi

doi:10.1109/IITC.2000.854266

New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS)

S. Kobayashi, M. Edahiro, Y. Hayashi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We present here the use of the performance predicting ECAD system, which is called Layout-design-based Interconnect Structure Optimization System (LADINOS), for the optimization of multilayer interconnect structures. This system is intended to be used to redesign current ULSI data on possible interconnect structures in the future and to measure the performance of such redesigned ULSIs. Despite the fact that system procedures include chip-size prediction, timing-driven assignment of interconnects to layers, and RC extraction which takes coupling capacitance into account, these procedures are performed very fast. We also give an example of the optimization of multi-layer interconnect structures for use in 0.13 μm-generation ULSIs with Al-interconnects.

Original language	English
Title of host publication	Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	12-14
Number of pages	3
ISBN (Electronic)	0780363272, 9780780363274
DOIs	https://doi.org/10.1109/IITC.2000.854266
Publication status	Published - 2000
Externally published	Yes
Event	3rd IEEE International Interconnect Technology Conference, IITC 2000 - Burlingame, United States Duration: 2000 Jun 5 → 2000 Jun 7

Publication series

Name	Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000

Conference

Conference	3rd IEEE International Interconnect Technology Conference, IITC 2000
Country/Territory	United States
City	Burlingame
Period	00/6/5 → 00/6/7

ASJC Scopus subject areas

Computer Science(all)

Access to Document

10.1109/IITC.2000.854266

Cite this

Kobayashi, S., Edahiro, M., & Hayashi, Y. (2000). New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS). In Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000 (pp. 12-14). Article 854266 (Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IITC.2000.854266

New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS). / Kobayashi, S.; Edahiro, M.; Hayashi, Y.
Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000. Institute of Electrical and Electronics Engineers Inc., 2000. p. 12-14 854266 (Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kobayashi, S, Edahiro, M & Hayashi, Y 2000, New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS). in Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000., 854266, Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000, Institute of Electrical and Electronics Engineers Inc., pp. 12-14, 3rd IEEE International Interconnect Technology Conference, IITC 2000, Burlingame, United States, 00/6/5. https://doi.org/10.1109/IITC.2000.854266

Kobayashi S, Edahiro M, Hayashi Y. New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS). In Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000. Institute of Electrical and Electronics Engineers Inc. 2000. p. 12-14. 854266. (Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000). doi: 10.1109/IITC.2000.854266

Kobayashi, S. ; Edahiro, M. ; Hayashi, Y. / New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS). Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000. Institute of Electrical and Electronics Engineers Inc., 2000. pp. 12-14 (Proceedings of the IEEE 2000 International Interconnect Technology Conference, IITC 2000).

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AB - We present here the use of the performance predicting ECAD system, which is called Layout-design-based Interconnect Structure Optimization System (LADINOS), for the optimization of multilayer interconnect structures. This system is intended to be used to redesign current ULSI data on possible interconnect structures in the future and to measure the performance of such redesigned ULSIs. Despite the fact that system procedures include chip-size prediction, timing-driven assignment of interconnects to layers, and RC extraction which takes coupling capacitance into account, these procedures are performed very fast. We also give an example of the optimization of multi-layer interconnect structures for use in 0.13 μm-generation ULSIs with Al-interconnects.

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New interconnect structure design methodology by Layout-design-based Interconnect Structure Optimization System (LADINOS)

Abstract

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