NEW METHOD FOR COMPACTION-BASED VLSI LAYOUT DESIGN.

Masaki Ishikawa; Tsuneo Matsuda; Takeshi Yoshimura; Satoshi Goto

NEW METHOD FOR COMPACTION-BASED VLSI LAYOUT DESIGN.

Masaki Ishikawa^*, Tsuneo Matsuda, Takeshi Yoshimura, Satoshi Goto

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

Abstract

The paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size, designed by using the proposed layout method, is only 1. 2 to approx 1. 4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective in achieving a minimal chip layout design.

Original language	English
Pages (from-to)	46-58
Number of pages	13
Journal	NEC Research and Development
Issue number	89
Publication status	Published - 1988 Apr
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "NEW METHOD FOR COMPACTION-BASED VLSI LAYOUT DESIGN.",

abstract = "The paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size, designed by using the proposed layout method, is only 1. 2 to approx 1. 4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective in achieving a minimal chip layout design.",

author = "Masaki Ishikawa and Tsuneo Matsuda and Takeshi Yoshimura and Satoshi Goto",

year = "1988",

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journal = "NEC Research and Development",

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AU - Ishikawa, Masaki

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PY - 1988/4

Y1 - 1988/4

N2 - The paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size, designed by using the proposed layout method, is only 1. 2 to approx 1. 4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective in achieving a minimal chip layout design.

AB - The paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size, designed by using the proposed layout method, is only 1. 2 to approx 1. 4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective in achieving a minimal chip layout design.

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NEW METHOD FOR COMPACTION-BASED VLSI LAYOUT DESIGN.

Abstract

ASJC Scopus subject areas

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