Abstract
It has been recognized that the building in reliability for hot-carrier is important in submicrometer p- MOSFET’s as well as n-MOSFET’s for use in the design of ULSI’s. Therefore in this paper, we introduce a new hot-carrier degradation model of p-MOSFET’s for bi-directional operation, aiming at constructing a new reliability simulator to cope with various operation modes. This model is based on the trap-induced barrier lowering (TIBL), the channel length modulation (CLM) due to electron traps in the oxide, and the mobility modulation (MM) due to interface state generation. By extracting these physically related parameters from transistor characteristics after hot-carrier injection in addition to extracting transistor model parameters before the injection, the hot-carrier degradation can be predicted not only in the linear and saturation regions but also in the forward and reverse operation modes.
| Original language | English |
|---|---|
| Pages (from-to) | 889-894 |
| Number of pages | 6 |
| Journal | Japanese journal of applied physics |
| Volume | 34 |
| Issue number | 2S |
| DOIs | |
| Publication status | Published - 1995 Feb |
| Externally published | Yes |
Keywords
- Bi-directional operation
- Electron trap
- Hot-carrier
- Interface state generation
- P-MOSFET
- Silicon
- Simulation
ASJC Scopus subject areas
- Engineering(all)
- Physics and Astronomy(all)