Novel and efficient min cut based voltage assignment in gate level

Tao Lin; Sheqin Dong; Song Chen; Yuchun Ma; Ou He; Satoshi Goto

doi:10.1109/ISQED.2011.5770719

Novel and efficient min cut based voltage assignment in gate level

Tao Lin^*, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto

^*Corresponding author for this work

Waseda University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

In this paper, we propose a novel min cut based algorithm for multiple supply voltage assignment under timing constraints. Different with the traditional sensitivity based methods which focus on how to make full use of the slacks of non-critical gates, the proposed algorithm concentrates on critical gates. The circuit is initialized in the lowest power level, then the length of critical paths is tried to be shortened with the minimized power increment until the timing constraints are satisfied. Experimental results show that given dual-vdd, our method beats traditional methods both in power saving and runtime, especially runtime.

Original language	English
Title of host publication	Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
Pages	150-155
Number of pages	6
DOIs	https://doi.org/10.1109/ISQED.2011.5770719
Publication status	Published - 2011
Event	12th International Symposium on Quality Electronic Design, ISQED 2011 - Santa Clara, CA Duration: 2011 Mar 14 → 2011 Mar 16

Other

Other	12th International Symposium on Quality Electronic Design, ISQED 2011
City	Santa Clara, CA
Period	11/3/14 → 11/3/16

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ISQED.2011.5770719

Cite this

Lin, T, Dong, S, Chen, S, Ma, Y, He, O & Goto, S 2011, Novel and efficient min cut based voltage assignment in gate level. in Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011., 5770719, pp. 150-155, 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, CA, 11/3/14. https://doi.org/10.1109/ISQED.2011.5770719

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abstract = "In this paper, we propose a novel min cut based algorithm for multiple supply voltage assignment under timing constraints. Different with the traditional sensitivity based methods which focus on how to make full use of the slacks of non-critical gates, the proposed algorithm concentrates on critical gates. The circuit is initialized in the lowest power level, then the length of critical paths is tried to be shortened with the minimized power increment until the timing constraints are satisfied. Experimental results show that given dual-vdd, our method beats traditional methods both in power saving and runtime, especially runtime.",

author = "Tao Lin and Sheqin Dong and Song Chen and Yuchun Ma and Ou He and Satoshi Goto",

year = "2011",

doi = "10.1109/ISQED.2011.5770719",

language = "English",

isbn = "9781612849140",

pages = "150--155",

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note = "12th International Symposium on Quality Electronic Design, ISQED 2011 ; Conference date: 14-03-2011 Through 16-03-2011",

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AU - Dong, Sheqin

AU - Chen, Song

AU - Ma, Yuchun

AU - He, Ou

AU - Goto, Satoshi

PY - 2011

Y1 - 2011

N2 - In this paper, we propose a novel min cut based algorithm for multiple supply voltage assignment under timing constraints. Different with the traditional sensitivity based methods which focus on how to make full use of the slacks of non-critical gates, the proposed algorithm concentrates on critical gates. The circuit is initialized in the lowest power level, then the length of critical paths is tried to be shortened with the minimized power increment until the timing constraints are satisfied. Experimental results show that given dual-vdd, our method beats traditional methods both in power saving and runtime, especially runtime.

AB - In this paper, we propose a novel min cut based algorithm for multiple supply voltage assignment under timing constraints. Different with the traditional sensitivity based methods which focus on how to make full use of the slacks of non-critical gates, the proposed algorithm concentrates on critical gates. The circuit is initialized in the lowest power level, then the length of critical paths is tried to be shortened with the minimized power increment until the timing constraints are satisfied. Experimental results show that given dual-vdd, our method beats traditional methods both in power saving and runtime, especially runtime.

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AN - SCOPUS:79959272905

SN - 9781612849140

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EP - 155

BT - Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

T2 - 12th International Symposium on Quality Electronic Design, ISQED 2011

Y2 - 14 March 2011 through 16 March 2011

ER -

Novel and efficient min cut based voltage assignment in gate level

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