On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

M. Fujii; H. Suzuki; H. Notani; H. Makino; H. Shinohara

doi:10.1109/ESSCIRC.2008.4681841

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

M. Fujii^*, H. Suzuki, H. Notani, H. Makino, H. Shinohara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper proposes on-chip leakage monitor circuit to scan optimal reversed body-biasing voltage (VBB) at which leakage current becomes minimal under gate induced drain leakage (GIDL) effect. The proposed circuit determines optimal VBB from the differential measurement of two replica circuit without absolute leakage current measurement. We fabricated this leakage monitor circuit in a 45nm-CMOS process. Measurement results shows 0.1 V resolution of VBB optimization.

Original language	English
Title of host publication	ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference
Pages	258-261
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2008.4681841
Publication status	Published - 2008
Externally published	Yes
Event	34th European Solid-State Circuits Conference, ESSCIRC 2008 - Edinburgh, Scotland, United Kingdom Duration: 2008 Sept 15 → 2008 Sept 19

Publication series

Name	ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Other

Other	34th European Solid-State Circuits Conference, ESSCIRC 2008
Country/Territory	United Kingdom
City	Edinburgh, Scotland
Period	08/9/15 → 08/9/19

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ESSCIRC.2008.4681841

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Fujii, M., Suzuki, H., Notani, H., Makino, H., & Shinohara, H. (2008). On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. In ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference (pp. 258-261). Article 4681841 (ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2008.4681841

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. / Fujii, M.; Suzuki, H.; Notani, H. et al.
ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference. 2008. p. 258-261 4681841 (ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fujii, M, Suzuki, H, Notani, H, Makino, H & Shinohara, H 2008, On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. in ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference., 4681841, ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference, pp. 258-261, 34th European Solid-State Circuits Conference, ESSCIRC 2008, Edinburgh, Scotland, United Kingdom, 08/9/15. https://doi.org/10.1109/ESSCIRC.2008.4681841

Fujii M, Suzuki H, Notani H, Makino H, Shinohara H. On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. In ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference. 2008. p. 258-261. 4681841. (ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference). doi: 10.1109/ESSCIRC.2008.4681841

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On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

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