TY - JOUR
T1 - On-chip multibit-test scheme for VLSI memories
AU - Hidaka, Hideto
AU - Fujishima, Kazuyasu
AU - Kumanoya, Masaki
AU - Miyatake, Hideshi
AU - Dosaka, Katsumi
AU - Nishimura, Yasumasa
AU - Yoshihara, Tsutomu
PY - 1988/9
Y1 - 1988/9
N2 - To reduce the time needed for testing VLSI memory chips, an on-chip multibit-test (MBT) scheme is proposed. The conditions for the test scheme and the relationship between the test mode and the memory array architecture (data bus structure, redundancy scheme, and so forth) are discussed. When the MBT mode is applied to the 1-Mbit DRAM, the increase in the chip area and power consumption are minimized, and the test for a 256-K bit device can be adopted to the memory array operating test. Using this technique, the time required for testing the device is reduced one-half to one-third.
AB - To reduce the time needed for testing VLSI memory chips, an on-chip multibit-test (MBT) scheme is proposed. The conditions for the test scheme and the relationship between the test mode and the memory array architecture (data bus structure, redundancy scheme, and so forth) are discussed. When the MBT mode is applied to the 1-Mbit DRAM, the increase in the chip area and power consumption are minimized, and the test for a 256-K bit device can be adopted to the memory array operating test. Using this technique, the time required for testing the device is reduced one-half to one-third.
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M3 - Article
AN - SCOPUS:0024071670
SN - 8756-663X
VL - 71
SP - 78
EP - 87
JO - Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
JF - Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
IS - 9
ER -