On-chip multibit-test scheme for VLSI memories

Hideto Hidaka*, Kazuyasu Fujishima, Masaki Kumanoya, Hideshi Miyatake, Katsumi Dosaka, Yasumasa Nishimura, Tsutomu Yoshihara

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


To reduce the time needed for testing VLSI memory chips, an on-chip multibit-test (MBT) scheme is proposed. The conditions for the test scheme and the relationship between the test mode and the memory array architecture (data bus structure, redundancy scheme, and so forth) are discussed. When the MBT mode is applied to the 1-Mbit DRAM, the increase in the chip area and power consumption are minimized, and the test for a 256-K bit device can be adopted to the memory array operating test. Using this technique, the time required for testing the device is reduced one-half to one-third.

Original languageEnglish
Pages (from-to)78-87
Number of pages10
JournalElectronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
Issue number9
Publication statusPublished - 1988 Sept
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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