Open-Source Hardware Memory Protection Engine Integrated with NVMM Simulator

Yu Omori, Keiji Kimura

Research output: Contribution to journalArticlepeer-review


With growing on-device IoT processing, security on edge devices becomes increasingly important. Among Trusted Execution Environment (TEE), an open-source RISC-V Keystone TEE is the expected one. However, some issues remain when applying it to various devices: untrusted DRAM, and untrusted path to non-volatile storage. These issues can be resolved by Memory Protection Engine (MPE) based on an integrity tree, and Non-Volatile Main Memory (NVMM), respectively. TEE, MPE, and NVMM must be cooperatively optimized to exploit performance. Despite this demand, there is no widely available platform which enables fast, reliable, and system-wide evaluation. In the paper, we provide an open-source hardware simulator for secure edge devices. We implemented an MPE using SGX-style Integrity Tree on the Keystone compatible RISC-V SoC. Then, we ported the NVMM simulation technique to it. Its whole design was publicized to widely provide a baseline hardware design. The MPE behavior was validated by using micro benchmarks. It revealed that the MPE read/write overhead is <inline-formula><tex-math notation="LaTeX">$2.55\times /4.16\times$</tex-math></inline-formula> on DRAM, and <inline-formula><tex-math notation="LaTeX">$3.05\times /5.40\times$</tex-math></inline-formula> on NVMM, respectively. Besides, we discuss our work&#x0027;s role by comparing with the gem5 considering TEE evaluation time and impact of the protected NVMM.

Original languageEnglish
Pages (from-to)1-4
Number of pages4
JournalIEEE Computer Architecture Letters
Publication statusAccepted/In press - 2022


  • Emulator
  • Encryption
  • Field programmable gate arrays
  • Hardware
  • Memory Encryption
  • Memory Integrity
  • Nonvolatile memory
  • NVMM
  • Open source software
  • Optimization
  • RISC-V
  • Simulator
  • System-on-chip

ASJC Scopus subject areas

  • Hardware and Architecture


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