Optimized 2-D SAD tree architecture of integer motion estimation for H.264/AVC

Yibo Fan*, Xiaoyang Zeng, Satoshi Goto

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


Integer Motion Estimation (IME) costs much computation in H.264/AVC video encoder. 2-D SAD tree IME architecture provides very high performance for encoder, and it has been used by many video codec designs. This paper proposes an optimized hardware design of 2-D SAD tree IME. Firstly, a new hardware architecture is proposed to reduce on-chip memory size. Secondly, a new search pattern is proposed to fully use memory bandwidth and reduce external memory access. Thirdly, the data-path is redesigned, and the performance is greatly improved. In order to compare with other IME designs, an IME design support D1 size, 30 fps with search range [±32, ±32] is implemented. The hardware cost of this design includes 118 KGates and 8Kb SRAM, the maximum clock frequency is 200 MHz. Compared to the original 2-D SAD tree IME, our design saves 87.5% on-chip memory, and achieves 3 times performance than original one. Our design provides a new way to design a low cost and high performance IME for H.264/AVC encoder.

Original languageEnglish
Pages (from-to)411-418
Number of pages8
JournalIEICE Transactions on Electronics
Issue number4
Publication statusPublished - 2011 Apr


  • 2-D SAD tree
  • H.264
  • IME

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials


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