Optimized design for high-performance megabit DRAMs

Masaki Kumanoya*, Katsumi Dosaka, Yashuhiro Konishi, Tsutomu Yoshihara, Hideshi Miyatake, Yuto Ikeda, Isao Furuta

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


Actual guidelines for the techniques to be employed for high-performance megabit DRAMs have been studied based on the performance analysis of conventional NMOS 1MDRAMs. The design technology to be employed for effective use of these new process techniques has been analyzed and optimized. CMOS 1MDRAMs were fabricated. The RAS access time at 5 V and 25°C was 50 ns with the current consumption of 28 mA (tc = 260 ns). Since the average standby current at a refresh interval of 64 ms was 80 μA, battery backup is possible in this high-performance 1MDRAM.

Original languageEnglish
Pages (from-to)14-23
Number of pages10
JournalElectronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
Issue number8
Publication statusPublished - 1989 Aug
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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