OSCAR compiler controlled multicore power reduction on android platform

Hideo Yamamoto*, Tomohiro Hirano, Kohei Muto, Hiroki Mikami, Takashi Goto, Dominic Hillenbrand, Moriyuki Takamura, Keiji Kimura, Hironori Kasahara

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In recent years, smart devices are transitioning from single core processors to multicore processors to satisfy the growing demands of higher performance and lower power consumption. However, power consumption of multicore processors is increasing, as usage of smart devices become more intense. This situation is one of the most fundamental and important obstacle that the mobile device industries face, to extend the battery life of smart devices. This paper evaluates the power reduction control by the OSCAR Automatic Parallelizing Compiler on an Android platform with the newly developed precise power measurement environment on the ODROID-X2, a development platform with the Samsung Exynos4412 Prime, which consists of 4 ARM Cortex-A9 cores. The OSCAR Compiler enables automatic exploitation of multigrain parallelism within a sequential program, and automatically generates a parallelized code with the OSCAR Multi-Platform API power reduction directives for the purpose of DVFS (Dynamic Voltage and Frequency Scaling), clock gating, and power gating. The paper also introduces a newly developed micro second order pseudo clock gating method to reduce power consumption using WFI (Wait For Interrupt). By inserting GPIO (General Purpose Input Output) control functions into programs, signals appear on the power waveform indicating the point of where the GPIO control was inserted and provides a precise power measurement of the specified program area. The results of the power evaluation for realtime Mpeg2 Decoder show 86.7% power reduction, namely from 2.79[W] to 0.37[W] and for real-time Optical Flow show 86.5% power reduction, namely from 2.23[W] to 0.36[W] on 3 core execution.

Original languageEnglish
Title of host publicationLanguages and Compilers for Parallel Computing - 26th International Workshop, LCPC 2013, Revised Selected Papers
EditorsCălin Caşcaval, Pablo Montesinos
PublisherSpringer Verlag
Pages155-168
Number of pages14
ISBN (Electronic)9783319099668
DOIs
Publication statusPublished - 2014
Event26th Workshop on Languages and Compilers for Parallel Computing, LCPC 2013 - San Jose, United States
Duration: 2013 Sept 252013 Sept 27

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume8664
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference26th Workshop on Languages and Compilers for Parallel Computing, LCPC 2013
Country/TerritoryUnited States
CitySan Jose
Period13/9/2513/9/27

Keywords

  • API
  • Android
  • Automatic parallelization
  • Multicore processor
  • Power control
  • Power reduction
  • Smart device
  • WFI

ASJC Scopus subject areas

  • Theoretical Computer Science
  • General Computer Science

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