Parallel enhanced low design effort H.264/AVC fractional motion estimation engine for super hi-vision application

Yiqing Huang; Takeshi Ikenaga

doi:10.1109/ASICON.2009.5351576

Parallel enhanced low design effort H.264/AVC fractional motion estimation engine for super hi-vision application

Yiqing Huang^*, Takeshi Ikenaga

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

One Super Hi-Vision (SHV) 4kx4k@60fps fractional motion estimation (FME) engine is proposed in this paper. Firstly, the mode reduction and edge detection techniques are adopted to filter out unpromising modes in the algorithm level. Secondly, two parallel improved schemes, called 16-pel scale processing and MB-split assignment, are given out in hardware level, which reduces design effort to only 217MHz. Moreover, sub-sampling technique is adopted during SATD (sum-of-absolute-transformed-difference) generation, which saves 75% hardware cost. By using TSMC O.18um in worst work conditions (1.62 V, 125° C), our FME engine can achieve SHV 4kx4k@60fps real-time processing with 547.5k gates hardware.

Original language	English
Title of host publication	ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
Pages	183-186
Number of pages	4
DOIs	https://doi.org/10.1109/ASICON.2009.5351576
Publication status	Published - 2009 Dec 1
Externally published	Yes
Event	2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China Duration: 2009 Oct 20 → 2009 Oct 23

Publication series

Name	ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Other

Other	2009 8th IEEE International Conference on ASIC, ASICON 2009
Country/Territory	China
City	Changsha
Period	09/10/20 → 09/10/23

Keywords

FME
H.264/AVC
Super Hi-Vision

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASICON.2009.5351576

Cite this

Huang, Y., & Ikenaga, T. (2009). Parallel enhanced low design effort H.264/AVC fractional motion estimation engine for super hi-vision application. In ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC (pp. 183-186). Article 5351576 (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC). https://doi.org/10.1109/ASICON.2009.5351576

Parallel enhanced low design effort H.264/AVC fractional motion estimation engine for super hi-vision application. / Huang, Yiqing; Ikenaga, Takeshi.
ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. 2009. p. 183-186 5351576 (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Huang, Y & Ikenaga, T 2009, Parallel enhanced low design effort H.264/AVC fractional motion estimation engine for super hi-vision application. in ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC., 5351576, ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, pp. 183-186, 2009 8th IEEE International Conference on ASIC, ASICON 2009, Changsha, China, 09/10/20. https://doi.org/10.1109/ASICON.2009.5351576

@inproceedings{8ed9397b9fc445e6b4e6944912f6a64c,

title = "Parallel enhanced low design effort H.264/AVC fractional motion estimation engine for super hi-vision application",

abstract = "One Super Hi-Vision (SHV) 4kx4k@60fps fractional motion estimation (FME) engine is proposed in this paper. Firstly, the mode reduction and edge detection techniques are adopted to filter out unpromising modes in the algorithm level. Secondly, two parallel improved schemes, called 16-pel scale processing and MB-split assignment, are given out in hardware level, which reduces design effort to only 217MHz. Moreover, sub-sampling technique is adopted during SATD (sum-of-absolute-transformed-difference) generation, which saves 75% hardware cost. By using TSMC O.18um in worst work conditions (1.62 V, 125° C), our FME engine can achieve SHV 4kx4k@60fps real-time processing with 547.5k gates hardware.",

keywords = "FME, H.264/AVC, Super Hi-Vision",

author = "Yiqing Huang and Takeshi Ikenaga",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/ASICON.2009.5351576",

language = "English",

isbn = "9781424438686",

series = "ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC",

pages = "183--186",

booktitle = "ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC",

note = "2009 8th IEEE International Conference on ASIC, ASICON 2009 ; Conference date: 20-10-2009 Through 23-10-2009",

}

TY - GEN

T1 - Parallel enhanced low design effort H.264/AVC fractional motion estimation engine for super hi-vision application

AU - Huang, Yiqing

AU - Ikenaga, Takeshi

PY - 2009/12/1

Y1 - 2009/12/1

N2 - One Super Hi-Vision (SHV) 4kx4k@60fps fractional motion estimation (FME) engine is proposed in this paper. Firstly, the mode reduction and edge detection techniques are adopted to filter out unpromising modes in the algorithm level. Secondly, two parallel improved schemes, called 16-pel scale processing and MB-split assignment, are given out in hardware level, which reduces design effort to only 217MHz. Moreover, sub-sampling technique is adopted during SATD (sum-of-absolute-transformed-difference) generation, which saves 75% hardware cost. By using TSMC O.18um in worst work conditions (1.62 V, 125° C), our FME engine can achieve SHV 4kx4k@60fps real-time processing with 547.5k gates hardware.

AB - One Super Hi-Vision (SHV) 4kx4k@60fps fractional motion estimation (FME) engine is proposed in this paper. Firstly, the mode reduction and edge detection techniques are adopted to filter out unpromising modes in the algorithm level. Secondly, two parallel improved schemes, called 16-pel scale processing and MB-split assignment, are given out in hardware level, which reduces design effort to only 217MHz. Moreover, sub-sampling technique is adopted during SATD (sum-of-absolute-transformed-difference) generation, which saves 75% hardware cost. By using TSMC O.18um in worst work conditions (1.62 V, 125° C), our FME engine can achieve SHV 4kx4k@60fps real-time processing with 547.5k gates hardware.

KW - FME

KW - H.264/AVC

KW - Super Hi-Vision

UR - http://www.scopus.com/inward/record.url?scp=77949392497&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77949392497&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2009.5351576

DO - 10.1109/ASICON.2009.5351576

M3 - Conference contribution

AN - SCOPUS:77949392497

SN - 9781424438686

T3 - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

SP - 183

EP - 186

BT - ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC

T2 - 2009 8th IEEE International Conference on ASIC, ASICON 2009

Y2 - 20 October 2009 through 23 October 2009

ER -

Parallel enhanced low design effort H.264/AVC fractional motion estimation engine for super hi-vision application

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this