Parallel HD encoding on cell

He Xun; Fang Xiangzhong; Wang Ci; Goto Satoshi

doi:10.1109/ISCAS.2009.5117943

Parallel HD encoding on cell

He Xun^*, Fang Xiangzhong, Wang Ci, Goto Satoshi

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

The Cell Broadband Engine Architecture (CBEA) is an excellent architecture for high performance distributed computing and multimedia processing. While the Cell/BE processor is capable of high definition H.264 encoding, there are still no such implementations available. In this paper, we present a parallel implementation of a HD H.264 encoder on this heterogeneous nine cores processor. First we implement a real time SD encoder on a single SPU by optimizing Motion Estimation algorithm, DMA transfers etc. Then we propose a pipelined parallel encoding algorithm for multicore processors, and use this algorithm to get a real time HD H.264 encoder (1920x1080@31fps) by using eight SPEs (58fps on 16 SPEs).

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Pages	1065-1068
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2009.5117943
Publication status	Published - 2009
Event	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei Duration: 2009 May 24 → 2009 May 27

Other

Other	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
City	Taipei
Period	09/5/24 → 09/5/27

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/ISCAS.2009.5117943

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title = "Parallel HD encoding on cell",

abstract = "The Cell Broadband Engine Architecture (CBEA) is an excellent architecture for high performance distributed computing and multimedia processing. While the Cell/BE processor is capable of high definition H.264 encoding, there are still no such implementations available. In this paper, we present a parallel implementation of a HD H.264 encoder on this heterogeneous nine cores processor. First we implement a real time SD encoder on a single SPU by optimizing Motion Estimation algorithm, DMA transfers etc. Then we propose a pipelined parallel encoding algorithm for multicore processors, and use this algorithm to get a real time HD H.264 encoder (1920x1080@31fps) by using eight SPEs (58fps on 16 SPEs).",

author = "He Xun and Fang Xiangzhong and Wang Ci and Goto Satoshi",

year = "2009",

doi = "10.1109/ISCAS.2009.5117943",

language = "English",

isbn = "9781424438280",

pages = "1065--1068",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

note = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 ; Conference date: 24-05-2009 Through 27-05-2009",

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T1 - Parallel HD encoding on cell

AU - Xun, He

AU - Xiangzhong, Fang

AU - Ci, Wang

AU - Satoshi, Goto

PY - 2009

Y1 - 2009

N2 - The Cell Broadband Engine Architecture (CBEA) is an excellent architecture for high performance distributed computing and multimedia processing. While the Cell/BE processor is capable of high definition H.264 encoding, there are still no such implementations available. In this paper, we present a parallel implementation of a HD H.264 encoder on this heterogeneous nine cores processor. First we implement a real time SD encoder on a single SPU by optimizing Motion Estimation algorithm, DMA transfers etc. Then we propose a pipelined parallel encoding algorithm for multicore processors, and use this algorithm to get a real time HD H.264 encoder (1920x1080@31fps) by using eight SPEs (58fps on 16 SPEs).

AB - The Cell Broadband Engine Architecture (CBEA) is an excellent architecture for high performance distributed computing and multimedia processing. While the Cell/BE processor is capable of high definition H.264 encoding, there are still no such implementations available. In this paper, we present a parallel implementation of a HD H.264 encoder on this heterogeneous nine cores processor. First we implement a real time SD encoder on a single SPU by optimizing Motion Estimation algorithm, DMA transfers etc. Then we propose a pipelined parallel encoding algorithm for multicore processors, and use this algorithm to get a real time HD H.264 encoder (1920x1080@31fps) by using eight SPEs (58fps on 16 SPEs).

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DO - 10.1109/ISCAS.2009.5117943

M3 - Conference contribution

AN - SCOPUS:70350138503

SN - 9781424438280

SP - 1065

EP - 1068

BT - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009

Y2 - 24 May 2009 through 27 May 2009

ER -

Parallel HD encoding on cell

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