Parallel Verification in RISC-V Secure Boot

Assuring the reliability of the OS boot process is essential to realize reliable computer systems. Secure Boot enables it by introducing the verification of the boot image with digital signature and hash values. This can be the basis for various security mechanisms. However, Secure Boot requires a long boot time due to their expensive computation costs, resulting in extended downtime. In this paper, we first implement Secure Boot in an ordinary RISC-V boot process on U-Boot, a representative open-source bootloader, and clarify the overhead introduced by the verification process. Based on the insight obtained above, we propose a parallelization of the verification process on a multi-core in Secure Boot. It accelerates the boot process while securely authenticating the boot image. We implement the proposed parallel verification process on U-Boot. The evaluation on a HiFive Unmatched RISC-V board shows that the parallelized hash computation on four cores achieves 3.96 times better performance than the original.