TY - GEN
T1 - Parallelizing compiler framework and API for power reduction and software productivity of real-time heterogeneous multicores
AU - Hayashi, Akihiro
AU - Wada, Yasutaka
AU - Watanabe, Takeshi
AU - Sekiguchi, Takeshi
AU - Mase, Masayoshi
AU - Shirako, Jun
AU - Kimura, Keiji
AU - Kasahara, Hironori
PY - 2011
Y1 - 2011
N2 - Heterogeneous multicores have been attracting much attention to attain high performance keeping power consumption low in wide spread of areas. However, heterogeneous multicores force programmers very difficult programming. The long application program development period lowers product competitiveness. In order to overcome such a situation, this paper proposes a compilation framework which bridges a gap between programmers and heterogeneous multicores. In particular, this paper describes the compilation framework based on OSCAR compiler. It realizes coarse grain task parallel processing, data transfer using a DMA controller, power reduction control from user programs with DVFS and clock gating on various heterogeneous multicores from different vendors. This paper also evaluates processing performance and the power reduction by the proposed framework on a newly developed 15 core heterogeneous multicore chip named RP-X integrating 8 general purpose processor cores and 3 types of accelerator cores which was developed by Renesas Electronics, Hitachi, Tokyo Institute of Technology and Waseda University. The framework attains speedups up to 32x for an optical flow program with eight general purpose processor cores and four DRP(Dynamically Reconfigurable Processor) accelerator cores against sequential execution by a single processor core and 80% of power reduction for the real-time AAC encoding.
AB - Heterogeneous multicores have been attracting much attention to attain high performance keeping power consumption low in wide spread of areas. However, heterogeneous multicores force programmers very difficult programming. The long application program development period lowers product competitiveness. In order to overcome such a situation, this paper proposes a compilation framework which bridges a gap between programmers and heterogeneous multicores. In particular, this paper describes the compilation framework based on OSCAR compiler. It realizes coarse grain task parallel processing, data transfer using a DMA controller, power reduction control from user programs with DVFS and clock gating on various heterogeneous multicores from different vendors. This paper also evaluates processing performance and the power reduction by the proposed framework on a newly developed 15 core heterogeneous multicore chip named RP-X integrating 8 general purpose processor cores and 3 types of accelerator cores which was developed by Renesas Electronics, Hitachi, Tokyo Institute of Technology and Waseda University. The framework attains speedups up to 32x for an optical flow program with eight general purpose processor cores and four DRP(Dynamically Reconfigurable Processor) accelerator cores against sequential execution by a single processor core and 80% of power reduction for the real-time AAC encoding.
KW - API
KW - Heterogeneous Multicore
KW - Parallelizing Compiler
UR - http://www.scopus.com/inward/record.url?scp=79952612610&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79952612610&partnerID=8YFLogxK
U2 - 10.1007/978-3-642-19595-2_13
DO - 10.1007/978-3-642-19595-2_13
M3 - Conference contribution
AN - SCOPUS:79952612610
SN - 9783642195945
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 184
EP - 198
BT - Languages and Compilers for Parallel Computing - 23rd International Workshop, LCPC 2010, Revised Selected Papers
T2 - 23rd International Workshop on Languages and Compilers for Parallel Computing, LCPC 2010
Y2 - 7 October 2010 through 9 October 2010
ER -