Parallelizing Factory Automation Ladder Programs by OSCAR Automatic Parallelizing Compiler

Programmable Logic Controllers (PLCs) and their programming language, or Ladder language, have been widely used for over 50 years to control plants like Factory Automation or FA. Demands for higher performance of Ladder programs on PLCs are increasing along with increasing functionality and complexity of plants, as well as growing numbers and variety of sensors and actuators. Traditional clock frequency improvement of a CPU in a PLC is inappropriate to satisfy them since high reliability and robustness are essential for plant control because of surrounding electrical noise. Instead, parallel processing on a multicore is a promising approach. However, Ladder programs have poor loop parallelism and basic block level fine task granularity. This paper proposes a parallelization technique of Ladder programs by the OSCAR automatic parallelizing compiler. It first translates a source Ladder program into an OSCAR compiler-friendly C program by a newly developed automatic translation tool. Then, the compiler parallelizes it. At the parallelization, the OSCAR compiler employs parallelism among macro tasks, each composed of a basic block in this application. However, the execution time of a basic block is relatively short compared with data transfer and synchronization overhead. Therefore, macro-task fusion is applied considering data dependency among macro tasks on a macro task graph so that the execution time of the fused macro task can be longer than the overhead and the parallelism among the fused macro tasks can be kept. Before the macro task fusion, the duplication of the basic block having a conditional branch and the graph transformation changing a macro task graph with control-dependence edges into a macro-task graph with just data dependence edges applied. Finally, the macro tasks on the macro task graph having data dependence edges are statically scheduled on processor cores. A performance evaluation on two ARM Cortex A53 cores on a Zynq UltraScale+ MPSoC ZCU102 shows the proposed technique can reduce 17% of execution clock cycles, though a parallel program before the proposed task fusion needs twice longer execution time on two cores against a sequential execution.