Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

Akira Ohchi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

doi:10.1109/ISCAS.2010.5537401

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

Akira Ohchi^*, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

^*Corresponding author for this work

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Functional units on a critical path use local registers and local controllers and functional units on non-critical path use shared register and global controller in our architecture. Our method is based on iterative improvement of scheduling/binding and floorplanning. Using iterative flow, we obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that 8.6% performance improvement can be achieved compared to the conventional high-performance method.

Original language	English
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Pages	921-924
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537401
Publication status	Published - 2010 Aug 31
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: 2010 May 30 → 2010 Jun 2

Publication series

Name	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Conference

Conference	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country/Territory	France
City	Paris
Period	10/5/30 → 10/6/2

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2010.5537401

Cite this

Ohchi, A., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2010). Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 921-924). Article 5537401 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537401

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. / Ohchi, Akira; Togawa, Nozomu ; Yanagisawa, Masao et al.
ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 921-924 5537401 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ohchi, A, Togawa, N , Yanagisawa, M & Ohtsuki, T 2010, Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537401, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, pp. 921-924, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 10/5/30. https://doi.org/10.1109/ISCAS.2010.5537401

Ohchi A, Togawa N , Yanagisawa M, Ohtsuki T. Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 921-924. 5537401. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). doi: 10.1109/ISCAS.2010.5537401

Ohchi, Akira ; Togawa, Nozomu ; Yanagisawa, Masao et al. / Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. pp. 921-924 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

@inproceedings{2faa0a92283f4037af411c69b5764618,

title = "Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation",

abstract = "In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Functional units on a critical path use local registers and local controllers and functional units on non-critical path use shared register and global controller in our architecture. Our method is based on iterative improvement of scheduling/binding and floorplanning. Using iterative flow, we obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that 8.6% performance improvement can be achieved compared to the conventional high-performance method.",

author = "Akira Ohchi and Nozomu Togawa and Masao Yanagisawa and Tatsuo Ohtsuki",

year = "2010",

month = aug,

day = "31",

doi = "10.1109/ISCAS.2010.5537401",

language = "English",

isbn = "9781424453085",

series = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems",

pages = "921--924",

booktitle = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems",

note = "2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 ; Conference date: 30-05-2010 Through 02-06-2010",

}

TY - GEN

T1 - Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

AU - Ohchi, Akira

AU - Togawa, Nozomu

AU - Yanagisawa, Masao

AU - Ohtsuki, Tatsuo

PY - 2010/8/31

Y1 - 2010/8/31

N2 - In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Functional units on a critical path use local registers and local controllers and functional units on non-critical path use shared register and global controller in our architecture. Our method is based on iterative improvement of scheduling/binding and floorplanning. Using iterative flow, we obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that 8.6% performance improvement can be achieved compared to the conventional high-performance method.

AB - In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Functional units on a critical path use local registers and local controllers and functional units on non-critical path use shared register and global controller in our architecture. Our method is based on iterative improvement of scheduling/binding and floorplanning. Using iterative flow, we obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that 8.6% performance improvement can be achieved compared to the conventional high-performance method.

UR - http://www.scopus.com/inward/record.url?scp=77955998595&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77955998595&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2010.5537401

DO - 10.1109/ISCAS.2010.5537401

M3 - Conference contribution

AN - SCOPUS:77955998595

SN - 9781424453085

T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

SP - 921

EP - 924

BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems

T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010

Y2 - 30 May 2010 through 2 June 2010

ER -

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this