Performance maximized interlayer via planning for 3D ICs

Jun Lu*, Song Chen, Takeshi Yoshimura

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)


As the development of semiconductor industry, 3D IC technology is introduced for its advantages in alleviating the interconnect problem coming with decreasing feature size and increasing integrated density. In 3D IC fabrication, one of the key challenges is the vertical connections between different device layers, which can be implemented by interlayer vias. In this paper, we proposed a performance-maximized interlayer via planning method for 3D ICs (multiple device layers), which can be used in the post-floorplanning stage.

Original languageEnglish
Title of host publicationASICON 2007 - 2007 7th International Conference on ASIC Proceeding
Number of pages4
Publication statusPublished - 2007
Event2007 7th International Conference on ASIC, ASICON 2007 - Guilin
Duration: 2007 Oct 262007 Oct 29


Other2007 7th International Conference on ASIC, ASICON 2007

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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