Abstract
As the development of semiconductor industry, 3D IC technology is introduced for its advantages in alleviating the interconnect problem coming with decreasing feature size and increasing integrated density. In 3D IC fabrication, one of the key challenges is the vertical connections between different device layers, which can be implemented by interlayer vias. In this paper, we proposed a performance-maximized interlayer via planning method for 3D ICs (multiple device layers), which can be used in the post-floorplanning stage.
| Original language | English |
|---|---|
| Title of host publication | ASICON 2007 - 2007 7th International Conference on ASIC Proceeding |
| Pages | 1096-1099 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2007 |
| Event | 2007 7th International Conference on ASIC, ASICON 2007 - Guilin Duration: 2007 Oct 26 → 2007 Oct 29 |
Other
| Other | 2007 7th International Conference on ASIC, ASICON 2007 |
|---|---|
| City | Guilin |
| Period | 07/10/26 → 07/10/29 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering