Permutation network for reconfigurable LDPC decoder based on banyan network

Xiao Peng*, Zhixiang Chen, Xiongxin Zhao, Fumiaki Maehara, Satoshi Goto

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


Since the structured quasi-cyclic low-density parity-check (QC-LDPC) codes for most modern wireless communication systems include multiple code rates, various block lengths, and the corresponding different sizes of submatrices in parity check matrix (PCM), the reconfigurable LDPC decoder is desirable and the permutation network is needed to accommodate any input number (IN) and shift number (SN) for cyclic shift. In this paper, we propose a novel permutation network architecture for the reconfigurable QC-LDPC decoders based on Banyan network. We prove that Banyan network has the nonblocking property for cyclic shift when the IN is power of 2, and give the control signal generating algorithm. Through introducing the bypass network, we put forward the nonblocking scheme for any IN and SN. In addition, we present the hardware design of the control signal generator, which can greatly reduce the hardware complexity and latency. The synthesis results using the TSMC 0.18 μm library demonstrate that the proposed permutation network can be implemented with the area of 0.546 mm2 and the frequency of 292 MHz.

Original languageEnglish
Pages (from-to)270-278
Number of pages9
JournalIEICE Transactions on Electronics
Issue number3
Publication statusPublished - 2010 Jan 1


  • Banyan network
  • LDPC decoder
  • Permutation
  • Reconfigurable

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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