Phase-adjustable Error Detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling

Masanori Kurimoto; Hiroaki Suzuki; Rei Akiyama; Tadao Yamanaka; Haruyuki Ohkuma; Hidehiro Takata; Hirofumi Shinohara

doi:10.1109/DAC.2008.4555944

Phase-adjustable Error Detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling

Masanori Kurimoto^*, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

Error Detection FFs for Dynamic Voltage Scaling (DVS) has been proposed. This technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. The error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the conventional DVS.

Original language	English
Title of host publication	Proceedings of the 45th Design Automation Conference, DAC
Pages	884-889
Number of pages	6
DOIs	https://doi.org/10.1109/DAC.2008.4555944
Publication status	Published - 2008 Sept 17
Externally published	Yes
Event	45th Design Automation Conference, DAC - Anaheim, CA, United States Duration: 2008 Jun 8 → 2008 Jun 13

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Other

Other	45th Design Automation Conference, DAC
Country/Territory	United States
City	Anaheim, CA
Period	08/6/8 → 08/6/13

Keywords

CTS
DVS
Error-Detection flip-flop
STA

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/DAC.2008.4555944

Cite this

Kurimoto, M., Suzuki, H., Akiyama, R., Yamanaka, T., Ohkuma, H., Takata, H., & Shinohara, H. (2008). Phase-adjustable Error Detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling. In Proceedings of the 45th Design Automation Conference, DAC (pp. 884-889). Article 4555944 (Proceedings - Design Automation Conference). https://doi.org/10.1109/DAC.2008.4555944

Phase-adjustable Error Detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling. / Kurimoto, Masanori; Suzuki, Hiroaki; Akiyama, Rei et al.
Proceedings of the 45th Design Automation Conference, DAC. 2008. p. 884-889 4555944 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kurimoto, M, Suzuki, H, Akiyama, R, Yamanaka, T, Ohkuma, H, Takata, H & Shinohara, H 2008, Phase-adjustable Error Detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling. in Proceedings of the 45th Design Automation Conference, DAC., 4555944, Proceedings - Design Automation Conference, pp. 884-889, 45th Design Automation Conference, DAC, Anaheim, CA, United States, 08/6/8. https://doi.org/10.1109/DAC.2008.4555944

Kurimoto M, Suzuki H, Akiyama R, Yamanaka T, Ohkuma H, Takata H et al. Phase-adjustable Error Detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling. In Proceedings of the 45th Design Automation Conference, DAC. 2008. p. 884-889. 4555944. (Proceedings - Design Automation Conference). doi: 10.1109/DAC.2008.4555944

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abstract = "Error Detection FFs for Dynamic Voltage Scaling (DVS) has been proposed. This technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. The error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the conventional DVS.",

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Phase-adjustable Error Detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling

Abstract

Publication series

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Keywords

ASJC Scopus subject areas

UN SDGs

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