Post-BIST fault diagnosis for multiple faults

Hiroshi Takahashi*, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


With the increasing complexity of LSI, Built-In Self Test (BIST) is a promising technique for production testing. We herein propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We refer to fault diagnosis based on the ambiguous test pattern set obtained by the compressed responses of BIST as post-BIST fault diagnosis [1]. In the present paper, we propose an effective method by which to perform post-BIST fault diagnosis for multiple stuck-at faults. The efficiency of the success ratio and the feasibility of diagnosing large circuits are discussed.

Original languageEnglish
Pages (from-to)771-775
Number of pages5
JournalIEICE Transactions on Information and Systems
Issue number3
Publication statusPublished - 2008 Mar
Externally publishedYes


  • Combinational circuits
  • Multiple stuck-at faults
  • Pass/fail information
  • Post-BIST fault diagnosis

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence


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