Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology

Hiroaki Suzuki; Masanori Kurimoto; Tadao Yamanaka; Hidehiro Takata; Hiroshi Makino; Hirofumi Shinohara

doi:10.1145/1393921.1393931

Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology

Hiroaki Suzuki^*, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technology era. The proposed platform measures device speed during post-fabrication testing. Then the fast die is marked so that the body-bias circuit turns on and reduces leakage current of the die that is selected and marked in a user application. Because the slow die around the speed specifications of a product is not body-biased, the product runs as fast as a normal non-body-biasing product. Although the leakage power of a fast die is reduced, the speed specification does not change. The proposed platform improves the worst corner specification comprising the two worst cases of speed and leakage power. The test chip, fabricated using 45-nm technology, improves the worst corner of stand-by leakage power vs. speed by 70%.

Original language	English
Title of host publication	ISLPED'08
Subtitle of host publication	Proceedings of the 2008 International Symposium on Low Power Electronics and Design
Pages	15-20
Number of pages	6
DOIs	https://doi.org/10.1145/1393921.1393931
Publication status	Published - 2008
Externally published	Yes
Event	ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design - Bangalore, India Duration: 2008 Aug 11 → 2008 Aug 13

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design
Country/Territory	India
City	Bangalore
Period	08/8/11 → 08/8/13

Keywords

Body-Biasing
Device variability suppression
Leakage current reduction
Post-Silicon Programming

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1145/1393921.1393931

Cite this

Suzuki, H., Kurimoto, M., Yamanaka, T., Takata, H., Makino, H., & Shinohara, H. (2008). Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology. In ISLPED'08: Proceedings of the 2008 International Symposium on Low Power Electronics and Design (pp. 15-20). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/1393921.1393931

Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology. / Suzuki, Hiroaki; Kurimoto, Masanori; Yamanaka, Tadao et al.
ISLPED'08: Proceedings of the 2008 International Symposium on Low Power Electronics and Design. 2008. p. 15-20 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Suzuki, H, Kurimoto, M, Yamanaka, T, Takata, H, Makino, H & Shinohara, H 2008, Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology. in ISLPED'08: Proceedings of the 2008 International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, pp. 15-20, ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design, Bangalore, India, 08/8/11. https://doi.org/10.1145/1393921.1393931

Suzuki H, Kurimoto M, Yamanaka T, Takata H, Makino H, Shinohara H. Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology. In ISLPED'08: Proceedings of the 2008 International Symposium on Low Power Electronics and Design. 2008. p. 15-20. (Proceedings of the International Symposium on Low Power Electronics and Design). doi: 10.1145/1393921.1393931

@inproceedings{547028c894014961b878723de250bf34,

title = "Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology",

abstract = "The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technology era. The proposed platform measures device speed during post-fabrication testing. Then the fast die is marked so that the body-bias circuit turns on and reduces leakage current of the die that is selected and marked in a user application. Because the slow die around the speed specifications of a product is not body-biased, the product runs as fast as a normal non-body-biasing product. Although the leakage power of a fast die is reduced, the speed specification does not change. The proposed platform improves the worst corner specification comprising the two worst cases of speed and leakage power. The test chip, fabricated using 45-nm technology, improves the worst corner of stand-by leakage power vs. speed by 70%.",

keywords = "Body-Biasing, Device variability suppression, Leakage current reduction, Post-Silicon Programming",

author = "Hiroaki Suzuki and Masanori Kurimoto and Tadao Yamanaka and Hidehiro Takata and Hiroshi Makino and Hirofumi Shinohara",

year = "2008",

doi = "10.1145/1393921.1393931",

language = "English",

isbn = "9781605581095",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

pages = "15--20",

booktitle = "ISLPED'08",

note = "ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design ; Conference date: 11-08-2008 Through 13-08-2008",

}

TY - GEN

T1 - Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology

AU - Suzuki, Hiroaki

AU - Kurimoto, Masanori

AU - Yamanaka, Tadao

AU - Takata, Hidehiro

AU - Makino, Hiroshi

AU - Shinohara, Hirofumi

PY - 2008

Y1 - 2008

N2 - The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technology era. The proposed platform measures device speed during post-fabrication testing. Then the fast die is marked so that the body-bias circuit turns on and reduces leakage current of the die that is selected and marked in a user application. Because the slow die around the speed specifications of a product is not body-biased, the product runs as fast as a normal non-body-biasing product. Although the leakage power of a fast die is reduced, the speed specification does not change. The proposed platform improves the worst corner specification comprising the two worst cases of speed and leakage power. The test chip, fabricated using 45-nm technology, improves the worst corner of stand-by leakage power vs. speed by 70%.

AB - The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technology era. The proposed platform measures device speed during post-fabrication testing. Then the fast die is marked so that the body-bias circuit turns on and reduces leakage current of the die that is selected and marked in a user application. Because the slow die around the speed specifications of a product is not body-biased, the product runs as fast as a normal non-body-biasing product. Although the leakage power of a fast die is reduced, the speed specification does not change. The proposed platform improves the worst corner specification comprising the two worst cases of speed and leakage power. The test chip, fabricated using 45-nm technology, improves the worst corner of stand-by leakage power vs. speed by 70%.

KW - Body-Biasing

KW - Device variability suppression

KW - Leakage current reduction

KW - Post-Silicon Programming

UR - http://www.scopus.com/inward/record.url?scp=57549087960&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=57549087960&partnerID=8YFLogxK

U2 - 10.1145/1393921.1393931

DO - 10.1145/1393921.1393931

M3 - Conference contribution

AN - SCOPUS:57549087960

SN - 9781605581095

T3 - Proceedings of the International Symposium on Low Power Electronics and Design

SP - 15

EP - 20

BT - ISLPED'08

T2 - ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design

Y2 - 11 August 2008 through 13 August 2008

ER -

Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology

Abstract

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Keywords

ASJC Scopus subject areas

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