Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

Taeko Matsunaga; Shinji Kimura; Yusuke Matsunaga

doi:10.1109/ISLPED.2011.5993639

Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

Taeko Matsunaga^*, Shinji Kimura, Yusuke Matsunaga

^*Corresponding author for this work

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Citations (Scopus)

Abstract

Recent researches have indicated that multi-operand addition on FPGAs can be efficiently realized as the architecture consisting of a compressor tree which reduces the number of operands and a carry-propagate adder like ASIC by utilizing generalized parallel counters(GPCs). This paper addresses power and delay aware synthesis of GPC-based compressor trees. Based on the observation that dynamic power would correlate to the number of GPCs and the levels of GPCs, our approach targets to minimize the maximum levels and the total number of GPCs, and an ILP-based algorithm and heuristic approaches are proposed. Several experiments targeting Altera Stratix III architecture show that the proposed approach reduced the delay by up to 20% under a slight increase in total power dissipation.

Original language	English
Title of host publication	IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Pages	217-222
Number of pages	6
DOIs	https://doi.org/10.1109/ISLPED.2011.5993639
Publication status	Published - 2011 Sept 19
Event	17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, Japan Duration: 2011 Aug 1 → 2011 Aug 3

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Country/Territory	Japan
City	Fukuoka
Period	11/8/1 → 11/8/3

ASJC Scopus subject areas

Engineering(all)

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10.1109/ISLPED.2011.5993639

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Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. / Matsunaga, Taeko; Kimura, Shinji; Matsunaga, Yusuke.
IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. 2011. p. 217-222 5993639 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Matsunaga, T, Kimura, S & Matsunaga, Y 2011, Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. in IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011., 5993639, Proceedings of the International Symposium on Low Power Electronics and Design, pp. 217-222, 17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011, Fukuoka, Japan, 11/8/1. https://doi.org/10.1109/ISLPED.2011.5993639

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abstract = "Recent researches have indicated that multi-operand addition on FPGAs can be efficiently realized as the architecture consisting of a compressor tree which reduces the number of operands and a carry-propagate adder like ASIC by utilizing generalized parallel counters(GPCs). This paper addresses power and delay aware synthesis of GPC-based compressor trees. Based on the observation that dynamic power would correlate to the number of GPCs and the levels of GPCs, our approach targets to minimize the maximum levels and the total number of GPCs, and an ILP-based algorithm and heuristic approaches are proposed. Several experiments targeting Altera Stratix III architecture show that the proposed approach reduced the delay by up to 20% under a slight increase in total power dissipation.",

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Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

Abstract

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