Power-aware compiler controllable chip multiprocessor

Hiroaki Shikano; Jun Shirako; Yasutaka Wada; Keiji Kimura; Hironori Kasahara

doi:10.1109/PACT.2007.4336255

Power-aware compiler controllable chip multiprocessor

Hiroaki Shikano^*, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

^*Corresponding author for this work

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Original language	English
Title of host publication	16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007
Pages	427
Number of pages	1
DOIs	https://doi.org/10.1109/PACT.2007.4336255
Publication status	Published - 2007
Event	16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007 - Brasov, Romania Duration: 2007 Sept 15 → 2007 Sept 19

Publication series

Name	Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
ISSN (Print)	1089-795X

Conference

Conference	16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007
Country/Territory	Romania
City	Brasov
Period	07/9/15 → 07/9/19

ASJC Scopus subject areas

Software
Theoretical Computer Science
Hardware and Architecture

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10.1109/PACT.2007.4336255

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Shikano, H., Shirako, J., Wada, Y., Kimura, K., & Kasahara, H. (2007). Power-aware compiler controllable chip multiprocessor. In 16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007 (pp. 427). Article 4336255 (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT). https://doi.org/10.1109/PACT.2007.4336255

Power-aware compiler controllable chip multiprocessor. / Shikano, Hiroaki; Shirako, Jun; Wada, Yasutaka et al.
16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007. 2007. p. 427 4336255 (Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shikano, H, Shirako, J, Wada, Y, Kimura, K & Kasahara, H 2007, Power-aware compiler controllable chip multiprocessor. in 16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007., 4336255, Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, pp. 427, 16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007, Brasov, Romania, 07/9/15. https://doi.org/10.1109/PACT.2007.4336255

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author = "Hiroaki Shikano and Jun Shirako and Yasutaka Wada and Keiji Kimura and Hironori Kasahara",

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language = "English",

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AU - Shirako, Jun

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T3 - Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

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Power-aware compiler controllable chip multiprocessor

Publication series

Conference

ASJC Scopus subject areas

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