Power-efficient LDPC code decoder architecture

Kazunori Shimizu; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto

doi:10.1145/1283780.1283858

Power-efficient LDPC code decoder architecture

Kazunori Shimizu^*, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression technique based on a clock gated shift register which reduces the read and write power dissipation for the intermediate messages. Simulation results show that the proposed decoder achieves 1.66 times faster decoding throughput, and improves the power efficiency (which is defined by the power dissipation per Mbps) up to 52% compared to the decoder based on the conventional overlapped schedule.

Original language	English
Title of host publication	ISLPED'07
Subtitle of host publication	Proceedings of the 2007 International Symposium on Low Power Electronics and Design
Pages	359-362
Number of pages	4
DOIs	https://doi.org/10.1145/1283780.1283858
Publication status	Published - 2007
Event	ISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR, United States Duration: 2007 Aug 27 → 2007 Aug 29

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Conference

Conference	ISLPED'07: 2007 International Symposium on Low Power Electronics and Design
Country/Territory	United States
City	Portland, OR
Period	07/8/27 → 07/8/29

Keywords

Clock gating
FIFO buffer
Intermediate message compression technique
LDPC decoder
Message-passing schedule

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1145/1283780.1283858

Cite this

Power-efficient LDPC code decoder architecture. / Shimizu, Kazunori; Togawa, Nozomu ; Ikenaga, Takeshi et al.
ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. 2007. p. 359-362 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shimizu, K, Togawa, N , Ikenaga, T & Goto, S 2007, Power-efficient LDPC code decoder architecture. in ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, pp. 359-362, ISLPED'07: 2007 International Symposium on Low Power Electronics and Design, Portland, OR, United States, 07/8/27. https://doi.org/10.1145/1283780.1283858

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title = "Power-efficient LDPC code decoder architecture",

abstract = "This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression technique based on a clock gated shift register which reduces the read and write power dissipation for the intermediate messages. Simulation results show that the proposed decoder achieves 1.66 times faster decoding throughput, and improves the power efficiency (which is defined by the power dissipation per Mbps) up to 52% compared to the decoder based on the conventional overlapped schedule.",

keywords = "Clock gating, FIFO buffer, Intermediate message compression technique, LDPC decoder, Message-passing schedule",

author = "Kazunori Shimizu and Nozomu Togawa and Takeshi Ikenaga and Satoshi Goto",

year = "2007",

doi = "10.1145/1283780.1283858",

language = "English",

isbn = "1595937099",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

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note = "ISLPED'07: 2007 International Symposium on Low Power Electronics and Design ; Conference date: 27-08-2007 Through 29-08-2007",

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AU - Shimizu, Kazunori

AU - Togawa, Nozomu

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2007

Y1 - 2007

N2 - This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression technique based on a clock gated shift register which reduces the read and write power dissipation for the intermediate messages. Simulation results show that the proposed decoder achieves 1.66 times faster decoding throughput, and improves the power efficiency (which is defined by the power dissipation per Mbps) up to 52% compared to the decoder based on the conventional overlapped schedule.

AB - This paper proposes the power-efficient LDPC decoder architecture which features (1) a FIFO buffering based rapid convergence schedule which enables the decoder to accelerate the decoding throughput without increasing the required number of memory bits, (2) an intermediate message compression technique based on a clock gated shift register which reduces the read and write power dissipation for the intermediate messages. Simulation results show that the proposed decoder achieves 1.66 times faster decoding throughput, and improves the power efficiency (which is defined by the power dissipation per Mbps) up to 52% compared to the decoder based on the conventional overlapped schedule.

KW - Clock gating

KW - FIFO buffer

KW - Intermediate message compression technique

KW - LDPC decoder

KW - Message-passing schedule

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T3 - Proceedings of the International Symposium on Low Power Electronics and Design

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Power-efficient LDPC code decoder architecture

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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