Power-efficient partitioning and cluster generation design for application-specific network-on-chip

Jiayi Ma; Cong Hao; Wencan Zhang; Takeshi Yoshimura

doi:10.1109/ISOCC.2016.7799744

Power-efficient partitioning and cluster generation design for application-specific network-on-chip

Jiayi Ma, Cong Hao, Wencan Zhang, Takeshi Yoshimura

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Network-on-Chip (NoC) is a promising solution for System-on-Chip (SoC) challenges. In this work, we present a Decompose and Cluster generation Refinement (DCR) algorithm to find minimum power consumption simultaneously. A two-stage method is proposed for decompose and cluster generation step to generate solutions with lower power. Refinement step explores optimal positions and adjusts clusters for selected solutions to find balanced point between power consumption and CPU time. Experimental results show that the proposed method outperforms the existing work.

Original language	English
Title of host publication	ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	83-84
Number of pages	2
ISBN (Electronic)	9781467393089
DOIs	https://doi.org/10.1109/ISOCC.2016.7799744
Publication status	Published - 2016 Dec 27
Event	13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26

Other

Other	13th International SoC Design Conference, ISOCC 2016
Country/Territory	Korea, Republic of
City	Jeju
Period	16/10/23 → 16/10/26

Keywords

Clustering
Network-on-chip
Partitioning

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/ISOCC.2016.7799744

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Power-efficient partitioning and cluster generation design for application-specific network-on-chip. / Ma, Jiayi; Hao, Cong; Zhang, Wencan et al.
ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 83-84 7799744.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ma, J, Hao, C, Zhang, W & Yoshimura, T 2016, Power-efficient partitioning and cluster generation design for application-specific network-on-chip. in ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things., 7799744, Institute of Electrical and Electronics Engineers Inc., pp. 83-84, 13th International SoC Design Conference, ISOCC 2016, Jeju, Korea, Republic of, 16/10/23. https://doi.org/10.1109/ISOCC.2016.7799744

@inproceedings{7233708e53184f27b9dfe1ece678477d,

title = "Power-efficient partitioning and cluster generation design for application-specific network-on-chip",

abstract = "Network-on-Chip (NoC) is a promising solution for System-on-Chip (SoC) challenges. In this work, we present a Decompose and Cluster generation Refinement (DCR) algorithm to find minimum power consumption simultaneously. A two-stage method is proposed for decompose and cluster generation step to generate solutions with lower power. Refinement step explores optimal positions and adjusts clusters for selected solutions to find balanced point between power consumption and CPU time. Experimental results show that the proposed method outperforms the existing work.",

keywords = "Clustering, Network-on-chip, Partitioning",

author = "Jiayi Ma and Cong Hao and Wencan Zhang and Takeshi Yoshimura",

year = "2016",

month = dec,

day = "27",

doi = "10.1109/ISOCC.2016.7799744",

language = "English",

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booktitle = "ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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note = "13th International SoC Design Conference, ISOCC 2016 ; Conference date: 23-10-2016 Through 26-10-2016",

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AU - Ma, Jiayi

AU - Hao, Cong

AU - Zhang, Wencan

AU - Yoshimura, Takeshi

PY - 2016/12/27

Y1 - 2016/12/27

N2 - Network-on-Chip (NoC) is a promising solution for System-on-Chip (SoC) challenges. In this work, we present a Decompose and Cluster generation Refinement (DCR) algorithm to find minimum power consumption simultaneously. A two-stage method is proposed for decompose and cluster generation step to generate solutions with lower power. Refinement step explores optimal positions and adjusts clusters for selected solutions to find balanced point between power consumption and CPU time. Experimental results show that the proposed method outperforms the existing work.

AB - Network-on-Chip (NoC) is a promising solution for System-on-Chip (SoC) challenges. In this work, we present a Decompose and Cluster generation Refinement (DCR) algorithm to find minimum power consumption simultaneously. A two-stage method is proposed for decompose and cluster generation step to generate solutions with lower power. Refinement step explores optimal positions and adjusts clusters for selected solutions to find balanced point between power consumption and CPU time. Experimental results show that the proposed method outperforms the existing work.

KW - Clustering

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KW - Partitioning

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U2 - 10.1109/ISOCC.2016.7799744

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M3 - Conference contribution

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SP - 83

EP - 84

BT - ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 13th International SoC Design Conference, ISOCC 2016

Y2 - 23 October 2016 through 26 October 2016

ER -

Power-efficient partitioning and cluster generation design for application-specific network-on-chip

Abstract

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Keywords

ASJC Scopus subject areas

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