Power reduction through specific instruction scheduling based on hardware/software Co-design

Zhao Kang; Bian Jinian; Jiang Chenqian; Dong Sheqin; Satoshi Goto

doi:10.1109/ICASIC.2007.4415600

Power reduction through specific instruction scheduling based on hardware/software Co-design

Zhao Kang^*, Bian Jinian, Jiang Chenqian, Dong Sheqin, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this paper, an instruction-level power reduction model for the low power System-on-a-Chip is proposed, which combines the hardware and software design together. Firstly, to reduce the power consumption via hardware design, this model is equipped with a specific instruction extraction process, which utilizes a sub-graph matching algorithm. Then a scheduling algorithm is integrated in this model to achieve power compression via reducing the memory access number. Finally, a set of Fir filter programs are power-driven optimized using the proposed model based on hardware/software co-design strategy, and the experimental results indicate that this model can reduce the power consumption effectively.

Original language	English
Title of host publication	ASICON 2007 - 2007 7th International Conference on ASIC Proceeding
Pages	193-196
Number of pages	4
DOIs	https://doi.org/10.1109/ICASIC.2007.4415600
Publication status	Published - 2007
Event	2007 7th International Conference on ASIC, ASICON 2007 - Guilin Duration: 2007 Oct 26 → 2007 Oct 29

Other

Other	2007 7th International Conference on ASIC, ASICON 2007
City	Guilin
Period	07/10/26 → 07/10/29

Keywords

Hardware/software co-design
Power reduction
Scheduling
SoC
Specific instruction

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ICASIC.2007.4415600

Cite this

@inproceedings{9f74a81a6589415cb0340c0100091027,

title = "Power reduction through specific instruction scheduling based on hardware/software Co-design",

abstract = "In this paper, an instruction-level power reduction model for the low power System-on-a-Chip is proposed, which combines the hardware and software design together. Firstly, to reduce the power consumption via hardware design, this model is equipped with a specific instruction extraction process, which utilizes a sub-graph matching algorithm. Then a scheduling algorithm is integrated in this model to achieve power compression via reducing the memory access number. Finally, a set of Fir filter programs are power-driven optimized using the proposed model based on hardware/software co-design strategy, and the experimental results indicate that this model can reduce the power consumption effectively.",

keywords = "Hardware/software co-design, Power reduction, Scheduling, SoC, Specific instruction",

author = "Zhao Kang and Bian Jinian and Jiang Chenqian and Dong Sheqin and Satoshi Goto",

year = "2007",

doi = "10.1109/ICASIC.2007.4415600",

language = "English",

isbn = "1424411327",

pages = "193--196",

booktitle = "ASICON 2007 - 2007 7th International Conference on ASIC Proceeding",

note = "2007 7th International Conference on ASIC, ASICON 2007 ; Conference date: 26-10-2007 Through 29-10-2007",

}

TY - GEN

T1 - Power reduction through specific instruction scheduling based on hardware/software Co-design

AU - Kang, Zhao

AU - Jinian, Bian

AU - Chenqian, Jiang

AU - Sheqin, Dong

AU - Goto, Satoshi

PY - 2007

Y1 - 2007

N2 - In this paper, an instruction-level power reduction model for the low power System-on-a-Chip is proposed, which combines the hardware and software design together. Firstly, to reduce the power consumption via hardware design, this model is equipped with a specific instruction extraction process, which utilizes a sub-graph matching algorithm. Then a scheduling algorithm is integrated in this model to achieve power compression via reducing the memory access number. Finally, a set of Fir filter programs are power-driven optimized using the proposed model based on hardware/software co-design strategy, and the experimental results indicate that this model can reduce the power consumption effectively.

AB - In this paper, an instruction-level power reduction model for the low power System-on-a-Chip is proposed, which combines the hardware and software design together. Firstly, to reduce the power consumption via hardware design, this model is equipped with a specific instruction extraction process, which utilizes a sub-graph matching algorithm. Then a scheduling algorithm is integrated in this model to achieve power compression via reducing the memory access number. Finally, a set of Fir filter programs are power-driven optimized using the proposed model based on hardware/software co-design strategy, and the experimental results indicate that this model can reduce the power consumption effectively.

KW - Hardware/software co-design

KW - Power reduction

KW - Scheduling

KW - SoC

KW - Specific instruction

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U2 - 10.1109/ICASIC.2007.4415600

DO - 10.1109/ICASIC.2007.4415600

M3 - Conference contribution

AN - SCOPUS:48349106572

SN - 1424411327

SN - 9781424411320

SP - 193

EP - 196

BT - ASICON 2007 - 2007 7th International Conference on ASIC Proceeding

T2 - 2007 7th International Conference on ASIC, ASICON 2007

Y2 - 26 October 2007 through 29 October 2007

ER -

Power reduction through specific instruction scheduling based on hardware/software Co-design

Abstract

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Keywords

ASJC Scopus subject areas

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