We propose an extraction method of process variation utilizing D-Flip-Flop (DFF) data retention characteristics and Ring Oscillator(RO) oscillation delay. Extracted process variation is modeled as PMOS and NMOS threshold voltage variations. Retention characteristics of the DFF circuit has different sensitivity to threshold voltage variation from the RO circuit. A DFF circuit is newly introduced as a complementary test structure of the conventional RO circuit for process variation extraction. By combining the RO circuit and the DFF circuits, we can accurately estimate the shift of global process variation. The test structure is implemented into silicon chip and the amount of global variation shift is extracted from measured data.
|Title of host publication
|ICMTS 2018 - Proceedings of the 2018 IEEE International Conference on Microelectronic Test Structures
|Institute of Electrical and Electronics Engineers Inc.
|Number of pages
|Published - 2018 Jun 12
|2018 IEEE International Conference on Microelectronic Test Structures, ICMTS 2018 - Austin, United States
Duration: 2018 Mar 19 → 2018 Mar 22
|IEEE International Conference on Microelectronic Test Structures
|2018 IEEE International Conference on Microelectronic Test Structures, ICMTS 2018
|18/3/19 → 18/3/22
ASJC Scopus subject areas
- Electrical and Electronic Engineering