TY - JOUR
T1 - Protograph-based LDPC coded system for position errors in racetrack memories
AU - Shibata, Ryo
AU - Hosoya, Gou
AU - Yashima, Hiroyuki
N1 - Funding Information:
This work was supported by JSPS KAKENHI Grant Numbers JP19K04400 and JP17K06443. The authors would like to thank the reviewers for their constructive comments that have helped improving the overall quality of the paper.
Publisher Copyright:
Copyright © 2019 The Institute of Electronics, Information and Communication Engineers.
PY - 2019
Y1 - 2019
N2 - In racetrack memories (RM), a position error (insertion or deletion error) results from unstable data reading. For position errors in RM with multiple read-heads (RHs), we propose a protograph-based LDPC coded system specified by a protograph and a protograph-aware permutation. The protograph-aware permutation facilitates the design and analysis of the coded system. By solving a multi-objective optimization problem, the coded system attains the properties of fast convergence decoding, a good decoding threshold, and a linear minimum distance growth. In addition, the coded system can adapt to varying numbers of RHs without any modification. The asymptotic decoding thresholds with a limited number of iterations verify the good properties of the system. Furthermore, for varying numbers of RHs, the simulation results with both small and large number of iterations, exhibit excellent decoding performances, both with short and long block lengths, and without error floors.
AB - In racetrack memories (RM), a position error (insertion or deletion error) results from unstable data reading. For position errors in RM with multiple read-heads (RHs), we propose a protograph-based LDPC coded system specified by a protograph and a protograph-aware permutation. The protograph-aware permutation facilitates the design and analysis of the coded system. By solving a multi-objective optimization problem, the coded system attains the properties of fast convergence decoding, a good decoding threshold, and a linear minimum distance growth. In addition, the coded system can adapt to varying numbers of RHs without any modification. The asymptotic decoding thresholds with a limited number of iterations verify the good properties of the system. Furthermore, for varying numbers of RHs, the simulation results with both small and large number of iterations, exhibit excellent decoding performances, both with short and long block lengths, and without error floors.
KW - Insertion/deletion channel
KW - LDPC code
KW - Position error
KW - Protograph
KW - Racetrack memory
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U2 - 10.1587/transfun.E102.A.1340
DO - 10.1587/transfun.E102.A.1340
M3 - Article
AN - SCOPUS:85073261717
SN - 0916-8508
VL - E102A
SP - 1340
EP - 1350
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IS - 10
ER -