TY - GEN
T1 - Reconciling application power control and operating systems for optimal power and performance
AU - Hillenbrand, Dominic
AU - Furuyama, Yuuki
AU - Hayashi, Akihiro
AU - Mikami, Hiroki
AU - Kimura, Keiji
AU - Kasahara, Hironori
N1 - Funding Information:
ACKNOWLEDGMENTS. We thank A. Jain for help with sample collection and library prep; the Cornell Genomics Facility for sequencing; N. Brown, D. Chen, Y. Hafezi,and A.-M.Jaksic for feedback regarding the experimental design; S.Misra for running the Western blot; E.Cosgrove for help with cluster analysis; I.Anreiter and M.Sokolowski for advice regarding foragingqPCR experiments.We thank the reviewers for their insightful suggestions and comments.A.G.C.and M.F.W.were supported by NIH award R01 HD059060. S.Y.N.D., S.V., A.G.C., M.T.W. and S.B. were supported by NIH award R01 GM135926. S.B. also acknowledges support from NIH award R21NS120227 and NSF award DMS-1812128.
PY - 2013
Y1 - 2013
N2 - In the age of dark silicon on-chip power control is a necessity. Upcoming and state of the art embedded- and cloud computer system-on-chips (SoCs) already provide interfaces for fine grained power control. Sometimes both: core- and interconnect-voltage and frequency can be scaled for example. To further reduce power consumption SoCs often have specialized accelerators. Due to the rising specialization of hard- and software general purpose operating systems require changes to exploit the power saving opportunities provided by the hardware. However, they lack detailed hardware- and application-level-information. Application-level power control in turn is still very uncommon and difficult to realize. Now a days vendors of mobile devices are forced to tweak and patch system-level software to enhance the power efficiency of each individual product. This manual process is time consuming and must be re-iterated for each new product. In this paper we explore the opportunities and challenges of automatic application- level power control using compilers.
AB - In the age of dark silicon on-chip power control is a necessity. Upcoming and state of the art embedded- and cloud computer system-on-chips (SoCs) already provide interfaces for fine grained power control. Sometimes both: core- and interconnect-voltage and frequency can be scaled for example. To further reduce power consumption SoCs often have specialized accelerators. Due to the rising specialization of hard- and software general purpose operating systems require changes to exploit the power saving opportunities provided by the hardware. However, they lack detailed hardware- and application-level-information. Application-level power control in turn is still very uncommon and difficult to realize. Now a days vendors of mobile devices are forced to tweak and patch system-level software to enhance the power efficiency of each individual product. This manual process is time consuming and must be re-iterated for each new product. In this paper we explore the opportunities and challenges of automatic application- level power control using compilers.
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U2 - 10.1109/ReCoSoC.2013.6581539
DO - 10.1109/ReCoSoC.2013.6581539
M3 - Conference contribution
AN - SCOPUS:84883679352
SN - 9781467361804
T3 - 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013
BT - 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013
T2 - 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013
Y2 - 10 July 2013 through 12 July 2013
ER -