Reducing Writing Energy Consumption for Non-Volatile Registers Utilizing Frequent Patterns of Sequential Bits on RISC-V Architecture

Single-board computers have been widely spread and used in a variety of situations, where they may be requested to operate under low-energy conditions or with an unstable power supply. Utilizing non-volatile memory (NVM) retaining data without power must be one of the effective solutions to tackle this issue. However, compared to volatile memory such as SRAM and DRAM, NVM consumes more energy in writing operations. In this paper, we propose an effective energy reduction method for RISC-V architecture, targeting one of NVMs called spin-transfer torque RAMs (STT-RAM). Firstly, we thoroughly investigate the writing bit patterns to registers in RISC-V architecture for various typical application programs and find out that most of them can be classified into three patterns, in which most bits in writing 32-bit data are 0s (zero's). Secondly, we propose an energy-reduced register-writing method utilizing these frequent writing bit patterns. In this method, when a writing data falls into one of the three frequent bit writing patterns above, we just write the bit pattern type into the extra bits and do not write actual data into registers and hence we can reduce the write energy in NVM register writing extremely. Experimental results on RISC-V architecture demonstrate that the energy consumption is reduced by 12.5%-53.8% by using our proposed method compared to the baseline architecture.