Region-oriented placement algorithm for coarse-grained power-gating FPGA architecture

Ce Li*, Yiping Dong, Takahiro Watanabe

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


An FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR [1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.

Original languageEnglish
Pages (from-to)314-323
Number of pages10
JournalIEICE Transactions on Information and Systems
Issue number2
Publication statusPublished - 2012 Feb
Externally publishedYes


  • FPGA
  • Hierarchical design
  • Low power
  • Power consumption
  • Region

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence


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