Abstract
Register allocation for instruction-level parallel processors involves problems that are not considered in register allocation for scalar processors. First, when the same register is allocated to different variables, anti-dependence is generated, which decreases instruction-level parallelism. Second, spill code should be inserted at a suitable position in its object, where it can be executed in parallel with other instructions. These problems do not exist for scalar processors, so existing register allocators take no account of them. This paper describes a new register allocation algorithm for solving these problems, using a graph structure that represents instructions and dependences between them.
| Original language | English |
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| Pages | 270-277 |
| Number of pages | 8 |
| Publication status | Published - 1996 |
| Event | Proceedings of the 1996 International Conference on Supercomputing - Philadelphia, PA, USA Duration: 1996 May 25 → 1996 May 28 |
Other
| Other | Proceedings of the 1996 International Conference on Supercomputing |
|---|---|
| City | Philadelphia, PA, USA |
| Period | 96/5/25 → 96/5/28 |
ASJC Scopus subject areas
- Computer Science(all)