RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

Masaki Kumanoya; Kazuyasu Fujishima; Hideshi Miyatake; Yasumasa Nishimura; Kazunori Saito; Takayuki Matsukawa; Tsutomu Yoshihara; Takao Nakano

RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

Masaki Kumanoya^*, Kazuyasu Fujishima, Hideshi Miyatake, Yasumasa Nishimura, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

Original language	English
Journal	IEEE Journal of Solid-State Circuits
Volume	SC-20
Issue number	5
Publication status	Published - 1985 Oct
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.",

abstract = "A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.",

author = "Masaki Kumanoya and Kazuyasu Fujishima and Hideshi Miyatake and Yasumasa Nishimura and Kazunori Saito and Takayuki Matsukawa and Tsutomu Yoshihara and Takao Nakano",

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T1 - RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

AU - Kumanoya, Masaki

AU - Fujishima, Kazuyasu

AU - Miyatake, Hideshi

AU - Nishimura, Yasumasa

AU - Saito, Kazunori

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

AU - Nakano, Takao

PY - 1985/10

Y1 - 1985/10

N2 - A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

AB - A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

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JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 5

ER -

RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

Abstract

ASJC Scopus subject areas

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