Residue BDD and its application to the verification of arithmetic circuits

Shinji Kimura

doi:10.1145/217474.217584

Residue BDD and its application to the verification of arithmetic circuits

Shinji Kimura^*

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

7 Citations (Scopus)

Abstract

The paper describes a verification method for arithmetic circuits based on residue arithmetic. In the verification, a residue module is attached to the specification and the implementation, and these outputs are compared by constructing BDD's. For the BDD construction without node explosion, we introduce a residue BDD whose width is less than or equal to a modulus. The method is useful for multipliers including C6288.

Original language	English
Pages (from-to)	542-545
Number of pages	4
Journal	Proceedings - Design Automation Conference
DOIs	https://doi.org/10.1145/217474.217584
Publication status	Published - 1995
Externally published	Yes
Event	Proceedings of the 32nd Design Automation Conference - San Francisco, CA, USA Duration: 1995 Jun 12 → 1995 Jun 16

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering

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10.1145/217474.217584

Cite this

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abstract = "The paper describes a verification method for arithmetic circuits based on residue arithmetic. In the verification, a residue module is attached to the specification and the implementation, and these outputs are compared by constructing BDD's. For the BDD construction without node explosion, we introduce a residue BDD whose width is less than or equal to a modulus. The method is useful for multipliers including C6288.",

author = "Shinji Kimura",

year = "1995",

doi = "10.1145/217474.217584",

language = "English",

pages = "542--545",

journal = "Proceedings - Design Automation Conference",

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PY - 1995

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N2 - The paper describes a verification method for arithmetic circuits based on residue arithmetic. In the verification, a residue module is attached to the specification and the implementation, and these outputs are compared by constructing BDD's. For the BDD construction without node explosion, we introduce a residue BDD whose width is less than or equal to a modulus. The method is useful for multipliers including C6288.

AB - The paper describes a verification method for arithmetic circuits based on residue arithmetic. In the verification, a residue module is attached to the specification and the implementation, and these outputs are compared by constructing BDD's. For the BDD construction without node explosion, we introduce a residue BDD whose width is less than or equal to a modulus. The method is useful for multipliers including C6288.

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U2 - 10.1145/217474.217584

DO - 10.1145/217474.217584

M3 - Conference article

AN - SCOPUS:0029224999

SN - 0738-100X

SP - 542

EP - 545

JO - Proceedings - Design Automation Conference

JF - Proceedings - Design Automation Conference

T2 - Proceedings of the 32nd Design Automation Conference

Y2 - 12 June 1995 through 16 June 1995

ER -

Residue BDD and its application to the verification of arithmetic circuits

Abstract

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