Residue BDD and its application to the verification of arithmetic circuits

Shinji Kimura*

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

7 Citations (Scopus)


The paper describes a verification method for arithmetic circuits based on residue arithmetic. In the verification, a residue module is attached to the specification and the implementation, and these outputs are compared by constructing BDD's. For the BDD construction without node explosion, we introduce a residue BDD whose width is less than or equal to a modulus. The method is useful for multipliers including C6288.

Original languageEnglish
Pages (from-to)542-545
Number of pages4
JournalProceedings - Design Automation Conference
Publication statusPublished - 1995
Externally publishedYes
EventProceedings of the 32nd Design Automation Conference - San Francisco, CA, USA
Duration: 1995 Jun 121995 Jun 16

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


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