Restructuring of memory hierarchy in computing system with spintronics-based technologies

Tetsuo Endoh*, Takashi Ohsawa, Hiroki Koike, Takahiro Hanyu, Hideo Ohno

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)


The restructuring of today's computer memory hierarchies that are caught in a dilemma between performance gain and power reduction is one of the most promising ways to making the computers much more efficient with much less power. To this end, several possibilities of using NV memories and NV logic with spin-transfer-torque magnetic tunnel junction (STT-MTJ) as levels in new hierarchies are discussed. A new NV-SRAM cell consisting of four transistors and two MTJs (4T-2MTJ) is shown to be a promising candidate for future NV-cache memories. For NV-main memories, we propose a PFET-based 1T-1MTJ cell combined with a new sense amplifier (S/A). A new NV-latch that can be constructed in flip-flops of synchronous core circuits is proposed and the world's fastest 600MHz operation is experimentally demonstrated.

Original languageEnglish
Title of host publication2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
Number of pages2
Publication statusPublished - 2012 Sept 27
Externally publishedYes
Event2012 Symposium on VLSI Technology, VLSIT 2012 - Honolulu, HI, United States
Duration: 2012 Jun 122012 Jun 14

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562


Other2012 Symposium on VLSI Technology, VLSIT 2012
Country/TerritoryUnited States
CityHonolulu, HI

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'Restructuring of memory hierarchy in computing system with spintronics-based technologies'. Together they form a unique fingerprint.

Cite this