Row-redundancy scheme for high-density flash memory

Masaaki Mihara; Takeshi Nakayama; Minoru Ohkawa; Shinji Kawai; Yoshikazu Milyawaki; Yesushi Tereda; Makoto Ohi; Hiroshi Onoda; Natsuo Ajika; Masahiro Hatanaka; Hirokazu Miyoshi; Tsutomu Yoshihara

Row-redundancy scheme for high-density flash memory

Masaaki Mihara^*, Takeshi Nakayama, Minoru Ohkawa, Shinji Kawai, Yoshikazu Milyawaki, Yesushi Tereda, Makoto Ohi, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

This paper describes the application of Gray code to the row decoder so that programming before erasure can be done to the defect word lines without incurring area penalty. Using this technique, a 3.3V operation 16Mb CMOS flash memory is fabricated in 0.5μm CMOS technology. The cell is 75ns at 3.3V Vcc. Process parameters and typical characteristics of the 16Mb memory are summarized. A block diagram of the chip is shown. The array is divided into 8 planes. Each plane is divided into four independently erasable 64kB blocks. There are 16 redundant WLs and 128 redundant columns. 65% of the repaired chips are confirmed by the proposed row redundancy system. Although the scheme is proven only by a limited number of devices, it apparently will be useful independent of the line level and the stage of manufacture. A micrograph of this chip is shown.

Original language	English
Title of host publication	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors	Anon
Place of Publication	Piscataway, NJ, United States
Publisher	Publ by IEEE
Pages	150-151
Number of pages	2
ISBN (Print)	0780318455
Publication status	Published - 1994
Externally published	Yes
Event	Proceedings of the 1994 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA Duration: 1994 Feb 16 → 1994 Feb 18

Other

Other	Proceedings of the 1994 IEEE International Solid-State Circuits Conference
City	San Francisco, CA, USA
Period	94/2/16 → 94/2/18

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Engineering(all)

Cite this

Mihara, M, Nakayama, T, Ohkawa, M, Kawai, S, Milyawaki, Y, Tereda, Y, Ohi, M, Onoda, H, Ajika, N, Hatanaka, M, Miyoshi, H & Yoshihara, T 1994, Row-redundancy scheme for high-density flash memory. in Anon (ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Publ by IEEE, Piscataway, NJ, United States, pp. 150-151, Proceedings of the 1994 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 94/2/16.

@inproceedings{80158f01c7174782906d9a6c57a333d4,

title = "Row-redundancy scheme for high-density flash memory",

abstract = "This paper describes the application of Gray code to the row decoder so that programming before erasure can be done to the defect word lines without incurring area penalty. Using this technique, a 3.3V operation 16Mb CMOS flash memory is fabricated in 0.5μm CMOS technology. The cell is 75ns at 3.3V Vcc. Process parameters and typical characteristics of the 16Mb memory are summarized. A block diagram of the chip is shown. The array is divided into 8 planes. Each plane is divided into four independently erasable 64kB blocks. There are 16 redundant WLs and 128 redundant columns. 65% of the repaired chips are confirmed by the proposed row redundancy system. Although the scheme is proven only by a limited number of devices, it apparently will be useful independent of the line level and the stage of manufacture. A micrograph of this chip is shown.",

author = "Masaaki Mihara and Takeshi Nakayama and Minoru Ohkawa and Shinji Kawai and Yoshikazu Milyawaki and Yesushi Tereda and Makoto Ohi and Hiroshi Onoda and Natsuo Ajika and Masahiro Hatanaka and Hirokazu Miyoshi and Tsutomu Yoshihara",

year = "1994",

language = "English",

isbn = "0780318455",

pages = "150--151",

editor = "Anon",

booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Publ by IEEE",

note = "Proceedings of the 1994 IEEE International Solid-State Circuits Conference ; Conference date: 16-02-1994 Through 18-02-1994",

}

TY - GEN

T1 - Row-redundancy scheme for high-density flash memory

AU - Mihara, Masaaki

AU - Nakayama, Takeshi

AU - Ohkawa, Minoru

AU - Kawai, Shinji

AU - Milyawaki, Yoshikazu

AU - Tereda, Yesushi

AU - Ohi, Makoto

AU - Onoda, Hiroshi

AU - Ajika, Natsuo

AU - Hatanaka, Masahiro

AU - Miyoshi, Hirokazu

AU - Yoshihara, Tsutomu

PY - 1994

Y1 - 1994

N2 - This paper describes the application of Gray code to the row decoder so that programming before erasure can be done to the defect word lines without incurring area penalty. Using this technique, a 3.3V operation 16Mb CMOS flash memory is fabricated in 0.5μm CMOS technology. The cell is 75ns at 3.3V Vcc. Process parameters and typical characteristics of the 16Mb memory are summarized. A block diagram of the chip is shown. The array is divided into 8 planes. Each plane is divided into four independently erasable 64kB blocks. There are 16 redundant WLs and 128 redundant columns. 65% of the repaired chips are confirmed by the proposed row redundancy system. Although the scheme is proven only by a limited number of devices, it apparently will be useful independent of the line level and the stage of manufacture. A micrograph of this chip is shown.

AB - This paper describes the application of Gray code to the row decoder so that programming before erasure can be done to the defect word lines without incurring area penalty. Using this technique, a 3.3V operation 16Mb CMOS flash memory is fabricated in 0.5μm CMOS technology. The cell is 75ns at 3.3V Vcc. Process parameters and typical characteristics of the 16Mb memory are summarized. A block diagram of the chip is shown. The array is divided into 8 planes. Each plane is divided into four independently erasable 64kB blocks. There are 16 redundant WLs and 128 redundant columns. 65% of the repaired chips are confirmed by the proposed row redundancy system. Although the scheme is proven only by a limited number of devices, it apparently will be useful independent of the line level and the stage of manufacture. A micrograph of this chip is shown.

UR - http://www.scopus.com/inward/record.url?scp=0028015196&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028015196&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0028015196

SN - 0780318455

SP - 150

EP - 151

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A2 - Anon, null

PB - Publ by IEEE

CY - Piscataway, NJ, United States

T2 - Proceedings of the 1994 IEEE International Solid-State Circuits Conference

Y2 - 16 February 1994 through 18 February 1994

ER -

Row-redundancy scheme for high-density flash memory

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