Row-redundancy scheme for high-density flash memory

Masaaki Mihara*, Takeshi Nakayama, Minoru Ohkawa, Shinji Kawai, Yoshikazu Milyawaki, Yesushi Tereda, Makoto Ohi, Hiroshi Onoda, Natsuo Ajika, Masahiro Hatanaka, Hirokazu Miyoshi, Tsutomu Yoshihara

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)


This paper describes the application of Gray code to the row decoder so that programming before erasure can be done to the defect word lines without incurring area penalty. Using this technique, a 3.3V operation 16Mb CMOS flash memory is fabricated in 0.5μm CMOS technology. The cell is 75ns at 3.3V Vcc. Process parameters and typical characteristics of the 16Mb memory are summarized. A block diagram of the chip is shown. The array is divided into 8 planes. Each plane is divided into four independently erasable 64kB blocks. There are 16 redundant WLs and 128 redundant columns. 65% of the repaired chips are confirmed by the proposed row redundancy system. Although the scheme is proven only by a limited number of devices, it apparently will be useful independent of the line level and the stage of manufacture. A micrograph of this chip is shown.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors Anon
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Number of pages2
ISBN (Print)0780318455
Publication statusPublished - 1994
Externally publishedYes
EventProceedings of the 1994 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1994 Feb 161994 Feb 18


OtherProceedings of the 1994 IEEE International Solid-State Circuits Conference
CitySan Francisco, CA, USA

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Engineering(all)


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