Abstract
The authors present a logic synthesis system based on a combined approach in which tables for transformation are described as rules and are applied by a rule interpreter together with a logic minimization algorithm. Physical constraints such as longest path lengths between registers, fan-in/out, and polarity are checked whenever each rule is applied. Experimental results show that the system generates solutions very close to the manual implementation, and a logic minimization algorithm reduces the circuit size by 20%.
Original language | English |
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Title of host publication | Unknown Host Publication Title |
Place of Publication | New York, NY, USA |
Publisher | IEEE |
Pages | 162-165 |
Number of pages | 4 |
ISBN (Print) | 0818607440 |
Publication status | Published - 1986 |
Externally published | Yes |
ASJC Scopus subject areas
- Engineering(all)