Scalable Hardware Efficient Architecture for Parallel FIR Filters with Symmetric Coefficients

Jinghao Ye, Masao Yanagisawa, Youhua Shi*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


Symmetric convolutions can be utilized for potential hardware resource reduction. However, they have not been realized in state-of-the-art transposed block FIR designs. Therefore, we explore the feasibility of symmetric convolution in transposed parallel FIRs and propose a scalable hardware efficient parallel architecture. The proposed design inserts delay elements after multipliers for temporal reuse of intermediate tap products. By doing this, the number of required multipliers can be reduced by half. As a result, we can achieve up to 3.2× and 1.64× area efficiency improvements over the modern transposed block method on reconfigurable and fixed designs, respectively. These results confirm the effectiveness of the proposed STB-FIR architecture for hardware-efficient, high-speed signal processing.

Original languageEnglish
Article number3272
JournalElectronics (Switzerland)
Issue number20
Publication statusPublished - 2022 Oct


  • FIR filter
  • hardware efficient
  • high-speed signal processing
  • symmetric transposed FIR

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Signal Processing
  • Hardware and Architecture
  • Computer Networks and Communications
  • Electrical and Electronic Engineering


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