Scaling scenario of floating body cell (FBC) suppressing Vth variation due to random dopant fluctuation

Hironobu Furuhashi*, Tomoaki Shino, Takashi Ohsawa, Fumiyoshi Matsuoka, Tomoki Higashi, Yoshihiro Minami, Hiroomi Nakajima, Katsuyuki Fujita, Ryo Fukuda, Takeshi Hamamoto, Akihiro Nitayama

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)


A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the Vth variation of cell array transistors is mainly attributed to the random dopant fluctuation in channel region. By setting the channel impurity concentration in the order of 1016cm-3 or lower, Gbit array functionality is guaranteed for the 32nm node and further scaled generations.

Original languageEnglish
Title of host publication2008 IEEE International SOI Conference Proceedings
Number of pages2
Publication statusPublished - 2008
Externally publishedYes
Event2008 IEEE International SOI Conference - New Paltz, NY, United States
Duration: 2008 Oct 62008 Oct 9

Publication series

NameProceedings - IEEE International SOI Conference
ISSN (Print)1078-621X


Other2008 IEEE International SOI Conference
Country/TerritoryUnited States
CityNew Paltz, NY

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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