Second-order polynomial expressions for on-chip interconnect capacitance

Atsushi Kurokawa; Masanori Hashimoto; Akira Kasebe; Zhangcai Huang; Yun Yang; Yasuaki Inoue; Ryosuke Inagaki; Hiroo Masuda

doi:10.1093/ietfec/e88-a.12.3453

Second-order polynomial expressions for on-chip interconnect capacitance

Atsushi Kurokawa^*, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

Original language	English
Pages (from-to)	3453-3460
Number of pages	8
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E88-A
Issue number	12
DOIs	https://doi.org/10.1093/ietfec/e88-a.12.3453
Publication status	Published - 2005 Dec

Keywords

Capacitance calculation
Capacitance extraction
Capacitance formula
Interconnect capacitance

ASJC Scopus subject areas

Electrical and Electronic Engineering
Hardware and Architecture
Information Systems

Access to Document

10.1093/ietfec/e88-a.12.3453

Cite this

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title = "Second-order polynomial expressions for on-chip interconnect capacitance",

abstract = "Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.",

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AU - Kurokawa, Atsushi

AU - Hashimoto, Masanori

AU - Kasebe, Akira

AU - Huang, Zhangcai

AU - Yang, Yun

AU - Inoue, Yasuaki

AU - Inagaki, Ryosuke

AU - Masuda, Hiroo

PY - 2005/12

Y1 - 2005/12

N2 - Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

AB - Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

KW - Capacitance calculation

KW - Capacitance extraction

KW - Capacitance formula

KW - Interconnect capacitance

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Second-order polynomial expressions for on-chip interconnect capacitance

Abstract

Keywords

ASJC Scopus subject areas

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