Second-order polynomial expressions for on-chip interconnect capacitance

Atsushi Kurokawa*, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    4 Citations (Scopus)


    Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

    Original languageEnglish
    Pages (from-to)3453-3460
    Number of pages8
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    Issue number12
    Publication statusPublished - 2005 Dec


    • Capacitance calculation
    • Capacitance extraction
    • Capacitance formula
    • Interconnect capacitance

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems


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