TY - GEN
T1 - Secure scan design using improved random order and its evaluations
AU - Oya, Masaru
AU - Atobe, Yuta
AU - Shi, Youhua
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
PY - 2015/2/5
Y1 - 2015/2/5
N2 - Scan test using scan chains is one of the most important DFT techniques. However, scan-based attacks are reported which can retrieve the secret key in crypto circuits by using scan chains. Secure scan architecture is strongly required to protect scan chains from scan-based attacks. This paper proposes an improved version of random order as a secure scan architecture. In improved random order, a scan chain is partitioned into multiple sub-chains. The structure of the scan chain changes dynamically by selecting a subchain to scan out. Testability and security of the proposed improved random order are also discussed in the paper, and the implementation results demonstrate the effectiveness of the proposed method.
AB - Scan test using scan chains is one of the most important DFT techniques. However, scan-based attacks are reported which can retrieve the secret key in crypto circuits by using scan chains. Secure scan architecture is strongly required to protect scan chains from scan-based attacks. This paper proposes an improved version of random order as a secure scan architecture. In improved random order, a scan chain is partitioned into multiple sub-chains. The structure of the scan chain changes dynamically by selecting a subchain to scan out. Testability and security of the proposed improved random order are also discussed in the paper, and the implementation results demonstrate the effectiveness of the proposed method.
KW - scan chains
KW - scan-based attack
KW - secure cryptro circuit
KW - secure scan architecture
UR - http://www.scopus.com/inward/record.url?scp=84937857893&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84937857893&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2014.7032842
DO - 10.1109/APCCAS.2014.7032842
M3 - Conference contribution
AN - SCOPUS:84937857893
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 555
EP - 558
BT - 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
Y2 - 17 November 2014 through 20 November 2014
ER -