Simplified 20-μm pitch vertical interconnection process for 3D chip stacking

Katsuyuki Sakuma*, Noriyasu Nagai, Mikiko Saito, Jun Mizuno, Shuichi Shoji

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

24 Citations (Scopus)


This paper describes a simplified vertical interconnection process for three-dimensional (3D) chip stacking. The unique feature of this new process is that the conductive filling material in the through-silicon-vias (TSVs), the microbumps, and the interconnection materials are all fabricated in one processing stage. All of the steps can be performed with the same piece of equipment. Prototype chips with 20-μm-pitch vertical interconnections have been demonstrated successfully. By using this technique, 75-μm deep high-aspect-ratio vias can be completely filled without voids using Ni electroplating and uniform 20-μm-pitch microbumps that are 4-μm tall have been fabricated using Sn-Cu electroplating.

Original languageEnglish
Pages (from-to)339-344
Number of pages6
JournalIEEJ Transactions on Electrical and Electronic Engineering
Issue number3
Publication statusPublished - 2009 May
Externally publishedYes


  • 3D integration
  • Electroplating
  • Lead-free solder
  • Microbump
  • Through-silicon-via (TSV)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'Simplified 20-μm pitch vertical interconnection process for 3D chip stacking'. Together they form a unique fingerprint.

Cite this