Skew-tolerant global synchronization based on periodically all-in-phase clocking for multi-core SOC platforms

Atsufumi Shibayama; Koichi Nose; Sunao Torii; Masayuki Mizuno; Masato Edahiro

doi:10.1109/VLSIC.2007.4342697

Skew-tolerant global synchronization based on periodically all-in-phase clocking for multi-core SOC platforms

Atsufumi Shibayama^*, Koichi Nose, Sunao Torii, Masayuki Mizuno, Masato Edahiro

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Citations (Scopus)

Abstract

A periodically all-in-phase clock generator and a skew-tolerant bus wrapper have been developed for multi-core SOC platforms. The clock generator produces clock frequencies in 81-steps, and the bus wrapper makes possible deterministic data transfer among different frequency clocks even when inter-clock skew is as high as 2 clock cycle times. A combination of the clock generator, the bus wrapper, arid loosely balanced global clock distribution serves to case chip-timing design while maintaining deterministic chip behavior.

Original language	English
Title of host publication	2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages	158-159
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIC.2007.4342697
Publication status	Published - 2007
Externally published	Yes
Event	2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan Duration: 2007 Jun 14 → 2007 Jun 16

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2007 Symposium on VLSI Circuits, VLSIC
Country/Territory	Japan
City	Kyoto
Period	07/6/14 → 07/6/16

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/VLSIC.2007.4342697

Cite this

Shibayama, A., Nose, K., Torii, S., Mizuno, M., & Edahiro, M. (2007). Skew-tolerant global synchronization based on periodically all-in-phase clocking for multi-core SOC platforms. In 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers (pp. 158-159). [4342697] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2007.4342697

Skew-tolerant global synchronization based on periodically all-in-phase clocking for multi-core SOC platforms. / Shibayama, Atsufumi; Nose, Koichi; Torii, Sunao et al.
2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. 2007. p. 158-159 4342697 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shibayama, A, Nose, K, Torii, S, Mizuno, M & Edahiro, M 2007, Skew-tolerant global synchronization based on periodically all-in-phase clocking for multi-core SOC platforms. in 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers., 4342697, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 158-159, 2007 Symposium on VLSI Circuits, VLSIC, Kyoto, Japan, 07/6/14. https://doi.org/10.1109/VLSIC.2007.4342697

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Skew-tolerant global synchronization based on periodically all-in-phase clocking for multi-core SOC platforms

Abstract

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ASJC Scopus subject areas

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