TY - GEN
T1 - Small-Area and Low-Power FPGA-Based Multipliers using Approximate Elementary Modules
AU - Guo, Yi
AU - Sun, Heming
AU - Kimura, Shinji
N1 - Funding Information:
organization between Waseda University and KIOXIA Corporation (former Toshiba Memory Corporation). The work was supported in part by Grants-Aid for Scientific Research from JSPS and a research fund from NEC. The work of Y. Guo was supported by the China Scholarship Council scholarship. The authors convey their sincere gratitude.
Publisher Copyright:
© 2020 IEEE.
PY - 2020/1
Y1 - 2020/1
N2 - Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications, because of its high performance, reconfigurability, and fast development. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics. The area and latency are significantly reduced by cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy requirements, eight configurations for approximate 8 × 8 multiplier are discussed. In terms of mean relative error distance (MRED), the accuracy loss of the proposed 8 × 8 multiplier is low as 0.17%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 20.36%. The critical path latency reduction is up to 27.66%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with com-parable accuracy.
AB - Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications, because of its high performance, reconfigurability, and fast development. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics. The area and latency are significantly reduced by cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy requirements, eight configurations for approximate 8 × 8 multiplier are discussed. In terms of mean relative error distance (MRED), the accuracy loss of the proposed 8 × 8 multiplier is low as 0.17%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 20.36%. The critical path latency reduction is up to 27.66%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with com-parable accuracy.
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U2 - 10.1109/ASP-DAC47756.2020.9045546
DO - 10.1109/ASP-DAC47756.2020.9045546
M3 - Conference contribution
AN - SCOPUS:85083039673
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 599
EP - 604
BT - ASP-DAC 2020 - 25th Asia and South Pacific Design Automation Conference, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020
Y2 - 13 January 2020 through 16 January 2020
ER -