SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

Katsuhiro Suma*, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Kazuyasy Fujishima, Yasuro Inoue, Tadashi Nishimura, Tsutomu Yoshihara

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)


The fundamental limitations of the SOI and bulk-Si DRAM are compared at 1.5V Vcc operation. The dependence of the read out signal amplitude on the memory cell storage capacitance (Cs) is shown. It is assumed that bit-line capacitance Cb of SOI structures i reduced by 25% compared with that of bulk-Si substrates. The mean value of data retention time in 256Mb DRAM should be longer than 5s at 80°C. For both memory cell structures, p-n junction leakage current is the dominant leakage mechanism. For 1.5V operation the lower limit of memory cell capacitance (Cs) from the data retention requirement is only 4.5fF for SOI, contrasted with 24fF for bulk-Si. This is because the junction area of SOI memory cell is reduced to 7.5% of bulk-Si DDRAM. Therefore thin-film SOL-DRAM provides a great advantage in data retention.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors Anon
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Number of pages2
ISBN (Print)0780318455
Publication statusPublished - 1994
Externally publishedYes
EventProceedings of the 1994 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1994 Feb 161994 Feb 18


OtherProceedings of the 1994 IEEE International Solid-State Circuits Conference
CitySan Francisco, CA, USA

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • General Engineering


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